diff mbox series

arm64: Subscribe Microsoft Azure Cobalt 100 to erratum 3194386

Message ID 20241003225239.321774-1-eahariha@linux.microsoft.com (mailing list archive)
State New, archived
Headers show
Series arm64: Subscribe Microsoft Azure Cobalt 100 to erratum 3194386 | expand

Commit Message

Easwar Hariharan Oct. 3, 2024, 10:52 p.m. UTC
Add the Microsoft Azure Cobalt 100 CPU to the list of CPUs suffering
from erratum 3194386 added in commit 75b3c43eab59 ("arm64: errata:
Expand speculative SSBS workaround")

CC: Mark Rutland <mark.rutland@arm.com>
CC: James More <james.morse@arm.com>
CC: Will Deacon <will@kernel.org>
CC: stable@vger.kernel.org # 6.6+
Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com>
---
 Documentation/arch/arm64/silicon-errata.rst | 2 ++
 arch/arm64/kernel/cpu_errata.c              | 1 +
 2 files changed, 3 insertions(+)

Comments

Catalin Marinas Oct. 4, 2024, 11:47 a.m. UTC | #1
On Thu, 03 Oct 2024 22:52:35 +0000, Easwar Hariharan wrote:
> Add the Microsoft Azure Cobalt 100 CPU to the list of CPUs suffering
> from erratum 3194386 added in commit 75b3c43eab59 ("arm64: errata:
> Expand speculative SSBS workaround")
> 
> 

Applied to arm64 (for-next/fixes), thanks!

[1/1] arm64: Subscribe Microsoft Azure Cobalt 100 to erratum 3194386
      https://git.kernel.org/arm64/c/3eddb108abe3
Easwar Hariharan Oct. 4, 2024, 4:24 p.m. UTC | #2
On 10/4/2024 4:47 AM, Catalin Marinas wrote:
> On Thu, 03 Oct 2024 22:52:35 +0000, Easwar Hariharan wrote:
>> Add the Microsoft Azure Cobalt 100 CPU to the list of CPUs suffering
>> from erratum 3194386 added in commit 75b3c43eab59 ("arm64: errata:
>> Expand speculative SSBS workaround")
>>
>>
> 
> Applied to arm64 (for-next/fixes), thanks!
> 
> [1/1] arm64: Subscribe Microsoft Azure Cobalt 100 to erratum 3194386
>       https://git.kernel.org/arm64/c/3eddb108abe3
> 

Thanks for queuing, I just saw that I typoed James' last name in the CC
of the commit message. i.e. it needs s/More/Morse/


I'll let you decide if it needs fixing up.

Thanks,
Easwar
Catalin Marinas Oct. 4, 2024, 4:31 p.m. UTC | #3
On Fri, Oct 04, 2024 at 09:24:15AM -0700, Easwar Hariharan wrote:
> On 10/4/2024 4:47 AM, Catalin Marinas wrote:
> > On Thu, 03 Oct 2024 22:52:35 +0000, Easwar Hariharan wrote:
> >> Add the Microsoft Azure Cobalt 100 CPU to the list of CPUs suffering
> >> from erratum 3194386 added in commit 75b3c43eab59 ("arm64: errata:
> >> Expand speculative SSBS workaround")
> > 
> > Applied to arm64 (for-next/fixes), thanks!
> > 
> > [1/1] arm64: Subscribe Microsoft Azure Cobalt 100 to erratum 3194386
> >       https://git.kernel.org/arm64/c/3eddb108abe3
> > 
> 
> Thanks for queuing, I just saw that I typoed James' last name in the CC
> of the commit message. i.e. it needs s/More/Morse/
> 
> I'll let you decide if it needs fixing up.

Too late, I already sent the pull request to Linus. I doubt anyone else
would notice ;).
diff mbox series

Patch

diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index 9eb5e70b4888..a7d03f1de72d 100644
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -289,3 +289,5 @@  stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | Microsoft      | Azure Cobalt 100| #2253138        | ARM64_ERRATUM_2253138       |
 +----------------+-----------------+-----------------+-----------------------------+
+| Microsoft      | Azure Cobalt 100| #3324339        | ARM64_ERRATUM_3194386       |
++----------------+-----------------+-----------------+-----------------------------+
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index dfefbdf4073a..1a6fd56a13c1 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -449,6 +449,7 @@  static const struct midr_range erratum_spec_ssbs_list[] = {
 	MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
 	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
 	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
+	MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
 	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
 	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
 	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),