| Message ID | 20241005064307.18972-2-quic_rdwivedi@quicinc.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Add support for multiple ICE algorithms | expand |
On Sat, 05 Oct 2024 12:13:05 +0530, Ram Kumar Dwivedi wrote: > There are three algorithms supported for inline crypto engine: > Floor based, Static and Instantaneous algorithm. > > Document the compatible used for the algorithm configurations > for inline crypto engine found. > > Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> > Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> > Co-developed-by: Nitin Rawat <quic_nitirawa@quicinc.com> > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com> > --- > .../devicetree/bindings/ufs/qcom,ufs.yaml | 24 +++++++++++++++++++ > 1 file changed, 24 insertions(+) > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/ufs/qcom,ufs.example.dtb: alg3: status: 'oneOf' conditional failed, one must be fixed: ['ok'] is not of type 'object' 'ok' is not one of ['okay', 'disabled', 'reserved', 'fail', 'fail-needs-probe'] from schema $id: http://devicetree.org/schemas/dt-core.yaml# doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241005064307.18972-2-quic_rdwivedi@quicinc.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On Sat, Oct 05, 2024 at 12:13:05PM +0530, Ram Kumar Dwivedi wrote: > There are three algorithms supported for inline crypto engine: > Floor based, Static and Instantaneous algorithm. > > Document the compatible used for the algorithm configurations > for inline crypto engine found. > > Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> > Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> > Co-developed-by: Nitin Rawat <quic_nitirawa@quicinc.com> > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com> > --- > .../devicetree/bindings/ufs/qcom,ufs.yaml | 24 +++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > index 25a5edeea164..5ac56e164643 100644 > --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > @@ -108,6 +108,11 @@ properties: > description: > GPIO connected to the RESET pin of the UFS memory device. > > + ice-config: > + type: object > + description: > + ICE configuration table for Qualcom SOC What goes in this node? > + > required: > - compatible > - reg > @@ -350,5 +355,24 @@ examples: > <0 0>, > <0 0>; > qcom,ice = <&ice>; > + > + ice_cfg: ice-config { > + alg1 { > + alg-name = "alg1"; > + rx-alloc-percent = <60>; > + status = "disabled"; Examples should be enabled. > + }; > + > + alg2 { > + alg-name = "alg2"; > + status = "disabled"; > + }; > + > + alg3 { > + alg-name = "alg3"; > + num-core = <28 28 15 13>; > + status = "ok"; > + }; > + }; > }; > }; > -- > 2.46.0 >
On Sat, Oct 05, 2024 at 12:13:05PM +0530, Ram Kumar Dwivedi wrote: > There are three algorithms supported for inline crypto engine: > Floor based, Static and Instantaneous algorithm. No. The algorithms supported by ICE are AES-XTS, AES-ECB, AES-CBC, etc. So I'm afraid this terminology is already taken. This new thing seems to be about how work is distributed among different hardware cores, so calling these "ICE schedulers" or something might make sense. - Eric
On 05/10/2024 08:43, Ram Kumar Dwivedi wrote: > There are three algorithms supported for inline crypto engine: > Floor based, Static and Instantaneous algorithm. > > Document the compatible used for the algorithm configurations > for inline crypto engine found. > > Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> > Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> > Co-developed-by: Nitin Rawat <quic_nitirawa@quicinc.com> > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com> Three people developed the code, but none of them cared to test it? Or make it even slightly correct? Sorry, this code is not ready for upstream. Please work internally on doing meaningful review and basic tests BEFORE posting. Best regards, Krzysztof
On 05-Oct-24 7:54 PM, Rob Herring (Arm) wrote: > > On Sat, 05 Oct 2024 12:13:05 +0530, Ram Kumar Dwivedi wrote: >> There are three algorithms supported for inline crypto engine: >> Floor based, Static and Instantaneous algorithm. >> >> Document the compatible used for the algorithm configurations >> for inline crypto engine found. >> >> Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> >> Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> >> Co-developed-by: Nitin Rawat <quic_nitirawa@quicinc.com> >> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> >> Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com> >> --- >> .../devicetree/bindings/ufs/qcom,ufs.yaml | 24 +++++++++++++++++++ >> 1 file changed, 24 insertions(+) >> > > My bot found errors running 'make dt_binding_check' on your patch: > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/ufs/qcom,ufs.example.dtb: alg3: status: 'oneOf' conditional failed, one must be fixed: > ['ok'] is not of type 'object' > 'ok' is not one of ['okay', 'disabled', 'reserved', 'fail', 'fail-needs-probe'] > from schema $id: http://devicetree.org/schemas/dt-core.yaml# > Hi Rob, I have addressed the comment in the latest patch set. Now the dt binding is successfully compiling. Thanks, Ram. > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241005064307.18972-2-quic_rdwivedi@quicinc.com > > The base for the series is generally the latest rc1. A different dependency > should be noted in *this* patch. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit after running the above command yourself. Note > that DT_SCHEMA_FILES can be set to your schema file to speed up checking > your schema. However, it must be unset to test all examples with your schema. >
On 06-Oct-24 12:45 AM, Eric Biggers wrote: > On Sat, Oct 05, 2024 at 12:13:05PM +0530, Ram Kumar Dwivedi wrote: >> There are three algorithms supported for inline crypto engine: >> Floor based, Static and Instantaneous algorithm. > > No. The algorithms supported by ICE are AES-XTS, AES-ECB, AES-CBC, etc. So I'm > afraid this terminology is already taken. > > This new thing seems to be about how work is distributed among different > hardware cores, so calling these "ICE schedulers" or something might make sense. > > - Eric Hi Eric, I have rephrased patch commit description. Used terminology as ICE allocator instead of ICE algorithm. Thanks, Ram.
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index 25a5edeea164..5ac56e164643 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -108,6 +108,11 @@ properties: description: GPIO connected to the RESET pin of the UFS memory device. + ice-config: + type: object + description: + ICE configuration table for Qualcom SOC + required: - compatible - reg @@ -350,5 +355,24 @@ examples: <0 0>, <0 0>; qcom,ice = <&ice>; + + ice_cfg: ice-config { + alg1 { + alg-name = "alg1"; + rx-alloc-percent = <60>; + status = "disabled"; + }; + + alg2 { + alg-name = "alg2"; + status = "disabled"; + }; + + alg3 { + alg-name = "alg3"; + num-core = <28 28 15 13>; + status = "ok"; + }; + }; }; };