| Message ID | 20241005221541.495844-1-richard.henderson@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | tcg/ppc: Use TCG_REG_TMP2 for scratch index in prepare_host_addr | expand |
06.10.2024 01:15, Richard Henderson wrote: > In tcg_out_qemu_ldst_i128, we need a non-zero index register, > which we then use as a base register in several address modes. > Since we always have TCG_REG_TMP2 available, use that. > > In tcg_out_qemu_st, in the fallback when STDBRX is not available, > avoid clobbering TCG_REG_TMP1, which might be h.base, which is > still in use. Use TCG_REG_TMP2 instead. Since the final use of > h.index is that ADDI, there is no conflict with the above. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2597 > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Fixes: v8.0.0-524-ge3867bad0d "tcg/ppc: Introduce HostAddress" Fixes: v8.0.0-744-g01a112e2e9 "tcg/ppc: Reorg tcg_out_tlb_read" Tested-By: Michael Tokarev <mjt@tls.msk.ru> Also noted for -stable. Thank you! /mjt
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 3f413ce3c1..223f079524 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2617,8 +2617,8 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { /* Zero-extend the guest address for use in the host address. */ - tcg_out_ext32u(s, TCG_REG_R0, addrlo); - h->index = TCG_REG_R0; + tcg_out_ext32u(s, TCG_REG_TMP2, addrlo); + h->index = TCG_REG_TMP2; } else { h->index = addrlo; } @@ -2704,9 +2704,9 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; if (!have_isa_2_06 && insn == STDBRX) { tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); - tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, h.index, 4)); + tcg_out32(s, ADDI | TAI(TCG_REG_TMP2, h.index, 4)); tcg_out_shri64(s, TCG_REG_R0, datalo, 32); - tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP1)); + tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP2)); } else { tcg_out32(s, insn | SAB(datalo, h.base, h.index)); }
In tcg_out_qemu_ldst_i128, we need a non-zero index register, which we then use as a base register in several address modes. Since we always have TCG_REG_TMP2 available, use that. In tcg_out_qemu_st, in the fallback when STDBRX is not available, avoid clobbering TCG_REG_TMP1, which might be h.base, which is still in use. Use TCG_REG_TMP2 instead. Since the final use of h.index is that ADDI, there is no conflict with the above. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2597 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/ppc/tcg-target.c.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)