Message ID | 1728313563-722267-2-git-send-email-radhey.shyam.pandey@amd.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Netdev Maintainers |
Headers | show |
Series | net: xilinx: emaclite: Adopt clock support | expand |
On Mon, Oct 07, 2024 at 08:36:01PM +0530, Radhey Shyam Pandey wrote: > From: Abin Joseph <abin.joseph@amd.com> > > Add s_axi_aclk AXI4 clock support. Traditionally this IP was used on > microblaze platforms which had fixed clocks enabled all the time. But > since its a PL IP, it can also be used on SoC platforms like Zynq > UltraScale+ MPSoC which combines processing system (PS) and user > programmable logic (PL) into the same device. On these platforms instead > of fixed enabled clocks it is mandatory to explicitly enable IP clocks > for proper functionality. > > So make clock a required property and also define max supported clock > constraints. > > Signed-off-by: Abin Joseph <abin.joseph@amd.com> > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Acked-by: Conor Dooley <conor.dooley@microchip.com>
diff --git a/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml b/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml index 92d8ade988f6..e16384aff557 100644 --- a/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml +++ b/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml @@ -29,6 +29,9 @@ properties: interrupts: maxItems: 1 + clocks: + maxItems: 1 + phy-handle: true local-mac-address: true @@ -45,6 +48,7 @@ required: - compatible - reg - interrupts + - clocks - phy-handle additionalProperties: false @@ -56,6 +60,7 @@ examples: reg = <0x40e00000 0x10000>; interrupt-parent = <&axi_intc_1>; interrupts = <1>; + clocks = <&dummy>; local-mac-address = [00 00 00 00 00 00]; phy-handle = <&phy0>; xlnx,rx-ping-pong;