diff mbox series

[v1,1/1] x86: Add support save/load HWCR MSR

Message ID 20240926040808.9158-1-gaoshiyuan@baidu.com (mailing list archive)
State New, archived
Headers show
Series [v1,1/1] x86: Add support save/load HWCR MSR | expand

Commit Message

Gao Shiyuan Sept. 26, 2024, 4:08 a.m. UTC 
KVM commit 191c8137a939 ("x86/kvm: Implement HWCR support")
introduced support for emulating HWCR MSR.

Add support for QEMU to save/load this MSR for migration purposes.

Signed-off-by: Gao Shiyuan <gaoshiyuan@baidu.com>
---
 target/i386/cpu.c     |  1 +
 target/i386/cpu.h     |  5 +++++
 target/i386/kvm/kvm.c | 12 ++++++++++++
 target/i386/machine.c | 20 ++++++++++++++++++++
 4 files changed, 38 insertions(+)

Comments

Zhijian Li (Fujitsu)" via Oct. 8, 2024, 2:47 a.m. UTC | #1 
Ping.

> KVM commit 191c8137a939 ("x86/kvm: Implement HWCR support")
> introduced support for emulating HWCR MSR.
>
> Add support for QEMU to save/load this MSR for migration purposes.
>
> Signed-off-by: Gao Shiyuan <gaoshiyuan@baidu.com>
> ---
> target/i386/cpu.c     |  1 +
> target/i386/cpu.h     |  5 +++++
> target/i386/kvm/kvm.c | 12 ++++++++++++
> target/i386/machine.c | 20 ++++++++++++++++++++
> 4 files changed, 38 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 85ef7452c0..339131a39a 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -7093,6 +7093,7 @@ static void x86_cpu_reset_hold(Object *obj, ResetType type)
>      env->a20_mask = ~0x0;
>      env->smbase = 0x30000;
>      env->msr_smi_count = 0;
> +    env->hwcr = 0;
>
>      env->idt.limit = 0xffff;
>      env->gdt.limit = 0xffff;
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 14edd57a37..a19b1ceda4 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -539,6 +539,8 @@ typedef enum X86Seg {
>
> #define MSR_AMD64_TSC_RATIO_DEFAULT     0x100000000ULL
>
> +#define MSR_K7_HWCR                     0xc0010015
> +
> #define MSR_VM_HSAVE_PA                 0xc0010117
>
> #define MSR_IA32_XFD                    0x000001c4
> @@ -1859,6 +1861,9 @@ typedef struct CPUArchState {
>      uint64_t msr_lbr_depth;
>      LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
>
> +    /* Hardware Configuration MSR */
> +    uint64_t hwcr;
> +
>      /* exception/interrupt handling */
>      int error_code;
>      int exception_is_int;
> diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
> index ada581c5d6..215c13eb13 100644
> --- a/target/i386/kvm/kvm.c
> +++ b/target/i386/kvm/kvm.c
> @@ -145,6 +145,7 @@ static bool has_msr_ucode_rev;
> static bool has_msr_vmx_procbased_ctls2;
> static bool has_msr_perf_capabs;
> static bool has_msr_pkrs;
> +static bool has_msr_hwcr;
>
> static uint32_t has_architectural_pmu_version;
> static uint32_t num_architectural_pmu_gp_counters;
> @@ -2554,6 +2555,8 @@ static int kvm_get_supported_msrs(KVMState *s)
>              case MSR_IA32_PKRS:
>                  has_msr_pkrs = true;
>                  break;
> +            case MSR_K7_HWCR:
> +                has_msr_hwcr = true;
>              }
>          }
>      }
> @@ -3824,6 +3827,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
>      if (has_msr_virt_ssbd) {
>          kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
>      }
> +    if (has_msr_hwcr) {
> +        kvm_msr_entry_add(cpu, MSR_K7_HWCR, env->hwcr);
> +    }
>
> #ifdef TARGET_X86_64
>      if (lm_capable_kernel) {
> @@ -4308,6 +4314,9 @@ static int kvm_get_msrs(X86CPU *cpu)
>          kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
>          env->tsc_valid = !runstate_is_running();
>      }
> +    if (has_msr_hwcr) {
> +        kvm_msr_entry_add(cpu, MSR_K7_HWCR, 0);
> +    }
>
> #ifdef TARGET_X86_64
>      if (lm_capable_kernel) {
> @@ -4827,6 +4836,9 @@ static int kvm_get_msrs(X86CPU *cpu)
>          case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31:
>              env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info = msrs[i].data;
>              break;
> +        case MSR_K7_HWCR:
> +            env->hwcr = msrs[i].data;
> +            break;
>          }
>      }
>
> diff --git a/target/i386/machine.c b/target/i386/machine.c
> index 39f8294f27..2db83acafa 100644
> --- a/target/i386/machine.c
> +++ b/target/i386/machine.c
> @@ -1543,6 +1543,25 @@ static const VMStateDescription vmstate_msr_xfd = {
>      }
> };
>
> +static bool msr_hwcr_needed(void *opaque)
> +{
> +    X86CPU *cpu = opaque;
> +    CPUX86State *env = &cpu->env;
> +
> +    return env->hwcr != 0;
> +}
> +
> +static const VMStateDescription vmstate_msr_hwcr = {
> +    .name = "cpu/msr_hwcr",
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .needed = msr_hwcr_needed,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_UINT64(env.hwcr, X86CPU),
> +        VMSTATE_END_OF_LIST()
> +    }
> +};
> +
> #ifdef TARGET_X86_64
> static bool intel_fred_msrs_needed(void *opaque)
> {
> @@ -1773,6 +1792,7 @@ const VMStateDescription vmstate_x86_cpu = {
>          &vmstate_msr_intel_sgx,
>          &vmstate_pdptrs,
>          &vmstate_msr_xfd,
> +        &vmstate_msr_hwcr,
> #ifdef TARGET_X86_64
>          &vmstate_msr_fred,
>          &vmstate_amx_xtile,
> --
> 2.34.1
Zhao Liu Oct. 9, 2024, 8:52 a.m. UTC | #2 
Hi Shiyuan,

On Thu, Sep 26, 2024 at 12:08:08PM +0800, Gao Shiyuan via wrote:
> Date: Thu, 26 Sep 2024 12:08:08 +0800
> From: Gao Shiyuan via <qemu-devel@nongnu.org>
> Subject: [PATCH v1 1/1] x86: Add support save/load HWCR MSR
> X-Mailer: git-send-email 2.39.3 (Apple Git-146)
> 
> KVM commit 191c8137a939 ("x86/kvm: Implement HWCR support")
> introduced support for emulating HWCR MSR.
> 
> Add support for QEMU to save/load this MSR for migration purposes.
> 
> Signed-off-by: Gao Shiyuan <gaoshiyuan@baidu.com>
> ---
>  target/i386/cpu.c     |  1 +
>  target/i386/cpu.h     |  5 +++++
>  target/i386/kvm/kvm.c | 12 ++++++++++++
>  target/i386/machine.c | 20 ++++++++++++++++++++
>  4 files changed, 38 insertions(+)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 85ef7452c0..339131a39a 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -7093,6 +7093,7 @@ static void x86_cpu_reset_hold(Object *obj, ResetType type)
>      env->a20_mask = ~0x0;
>      env->smbase = 0x30000;
>      env->msr_smi_count = 0;
> +    env->hwcr = 0;

Why we need to clear it here? This needs to be explained in the commit
message.

>      env->idt.limit = 0xffff;
>      env->gdt.limit = 0xffff;
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 14edd57a37..a19b1ceda4 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -539,6 +539,8 @@ typedef enum X86Seg {
>  
>  #define MSR_AMD64_TSC_RATIO_DEFAULT     0x100000000ULL
>  
> +#define MSR_K7_HWCR                     0xc0010015
> +
>  #define MSR_VM_HSAVE_PA                 0xc0010117
>  
>  #define MSR_IA32_XFD                    0x000001c4
> @@ -1859,6 +1861,9 @@ typedef struct CPUArchState {
>      uint64_t msr_lbr_depth;
>      LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
>  
> +    /* Hardware Configuration MSR */

We can keep the same comment as msr_hwcr in KVM to emphasize this is an
AMD-specific MSR, i.e.,

/* AMD MSRC001_0015 Hardware Configuration */

> +    uint64_t hwcr;

Add the msr_ prefix to indicate that this value is only intended to
store the MSR. Currently, for similar members, some have the msr_ prefix
and some do not, but it is better to have it for clarity.

> +
>      /* exception/interrupt handling */
>      int error_code;
>      int exception_is_int;

-Zhao
diff mbox series

Patch

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 85ef7452c0..339131a39a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7093,6 +7093,7 @@  static void x86_cpu_reset_hold(Object *obj, ResetType type)
     env->a20_mask = ~0x0;
     env->smbase = 0x30000;
     env->msr_smi_count = 0;
+    env->hwcr = 0;
 
     env->idt.limit = 0xffff;
     env->gdt.limit = 0xffff;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 14edd57a37..a19b1ceda4 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -539,6 +539,8 @@  typedef enum X86Seg {
 
 #define MSR_AMD64_TSC_RATIO_DEFAULT     0x100000000ULL
 
+#define MSR_K7_HWCR                     0xc0010015
+
 #define MSR_VM_HSAVE_PA                 0xc0010117
 
 #define MSR_IA32_XFD                    0x000001c4
@@ -1859,6 +1861,9 @@  typedef struct CPUArchState {
     uint64_t msr_lbr_depth;
     LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
 
+    /* Hardware Configuration MSR */
+    uint64_t hwcr;
+
     /* exception/interrupt handling */
     int error_code;
     int exception_is_int;
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index ada581c5d6..215c13eb13 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -145,6 +145,7 @@  static bool has_msr_ucode_rev;
 static bool has_msr_vmx_procbased_ctls2;
 static bool has_msr_perf_capabs;
 static bool has_msr_pkrs;
+static bool has_msr_hwcr;
 
 static uint32_t has_architectural_pmu_version;
 static uint32_t num_architectural_pmu_gp_counters;
@@ -2554,6 +2555,8 @@  static int kvm_get_supported_msrs(KVMState *s)
             case MSR_IA32_PKRS:
                 has_msr_pkrs = true;
                 break;
+            case MSR_K7_HWCR:
+                has_msr_hwcr = true;
             }
         }
     }
@@ -3824,6 +3827,9 @@  static int kvm_put_msrs(X86CPU *cpu, int level)
     if (has_msr_virt_ssbd) {
         kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
     }
+    if (has_msr_hwcr) {
+        kvm_msr_entry_add(cpu, MSR_K7_HWCR, env->hwcr);
+    }
 
 #ifdef TARGET_X86_64
     if (lm_capable_kernel) {
@@ -4308,6 +4314,9 @@  static int kvm_get_msrs(X86CPU *cpu)
         kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
         env->tsc_valid = !runstate_is_running();
     }
+    if (has_msr_hwcr) {
+        kvm_msr_entry_add(cpu, MSR_K7_HWCR, 0);
+    }
 
 #ifdef TARGET_X86_64
     if (lm_capable_kernel) {
@@ -4827,6 +4836,9 @@  static int kvm_get_msrs(X86CPU *cpu)
         case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31:
             env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info = msrs[i].data;
             break;
+        case MSR_K7_HWCR:
+            env->hwcr = msrs[i].data;
+            break;
         }
     }
 
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 39f8294f27..2db83acafa 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -1543,6 +1543,25 @@  static const VMStateDescription vmstate_msr_xfd = {
     }
 };
 
+static bool msr_hwcr_needed(void *opaque)
+{
+    X86CPU *cpu = opaque;
+    CPUX86State *env = &cpu->env;
+
+    return env->hwcr != 0;
+}
+
+static const VMStateDescription vmstate_msr_hwcr = {
+    .name = "cpu/msr_hwcr",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = msr_hwcr_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(env.hwcr, X86CPU),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 #ifdef TARGET_X86_64
 static bool intel_fred_msrs_needed(void *opaque)
 {
@@ -1773,6 +1792,7 @@  const VMStateDescription vmstate_x86_cpu = {
         &vmstate_msr_intel_sgx,
         &vmstate_pdptrs,
         &vmstate_msr_xfd,
+        &vmstate_msr_hwcr,
 #ifdef TARGET_X86_64
         &vmstate_msr_fred,
         &vmstate_amx_xtile,