| Message ID | 20240929093418.526901-1-yujiaoliang@vivo.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v1] mmc: Fix typos in comments across various files | expand |
On Sun, Sep 29, 2024 at 11:52 AM Yu Jiaoliang <yujiaoliang@vivo.com> wrote: > > This patch corrects several typos in comments within the mmc/host > directory. No functional changes are introduced, only comment > improvements for better readability. > > Detected using codespell. > > Signed-off-by: Yu Jiaoliang <yujiaoliang@vivo.com> > --- > drivers/mmc/host/atmel-mci.c | 2 +- > drivers/mmc/host/au1xmmc.c | 2 +- > drivers/mmc/host/cavium-octeon.c | 2 +- > drivers/mmc/host/dw_mmc.c | 2 +- > drivers/mmc/host/meson-gx-mmc.c | 2 +- for meson-gx-mmc: Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
On Sun, 29 Sept 2024 at 11:34, Yu Jiaoliang <yujiaoliang@vivo.com> wrote: > > This patch corrects several typos in comments within the mmc/host > directory. No functional changes are introduced, only comment > improvements for better readability. > > Detected using codespell. > > Signed-off-by: Yu Jiaoliang <yujiaoliang@vivo.com> Applied for next, thanks! Kind regards Uffe > --- > drivers/mmc/host/atmel-mci.c | 2 +- > drivers/mmc/host/au1xmmc.c | 2 +- > drivers/mmc/host/cavium-octeon.c | 2 +- > drivers/mmc/host/dw_mmc.c | 2 +- > drivers/mmc/host/meson-gx-mmc.c | 2 +- > drivers/mmc/host/mmci.h | 2 +- > drivers/mmc/host/sdhci-esdhc-imx.c | 4 ++-- > drivers/mmc/host/sdhci-msm.c | 2 +- > 8 files changed, 9 insertions(+), 9 deletions(-) > > diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c > index 6490df54a6f5..f444ca5dd154 100644 > --- a/drivers/mmc/host/atmel-mci.c > +++ b/drivers/mmc/host/atmel-mci.c > @@ -860,7 +860,7 @@ static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) > } > > /* > - * Configure given PDC buffer taking care of alignement issues. > + * Configure given PDC buffer taking care of alignment issues. > * Update host->data_size and host->sg. > */ > static void atmci_pdc_set_single_buf(struct atmel_mci *host, > diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c > index 6e80bcb668ec..7393d2ea5e57 100644 > --- a/drivers/mmc/host/au1xmmc.c > +++ b/drivers/mmc/host/au1xmmc.c > @@ -543,7 +543,7 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) > cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24; > } > } else { > - /* Techincally, we should be getting all 48 bits of > + /* Technically, we should be getting all 48 bits of > * the response (SD_RESP1 + SD_RESP2), but because > * our response omits the CRC, our data ends up > * being shifted 8 bits to the right. In this case, > diff --git a/drivers/mmc/host/cavium-octeon.c b/drivers/mmc/host/cavium-octeon.c > index 060ec4f4800f..d150d83b41ed 100644 > --- a/drivers/mmc/host/cavium-octeon.c > +++ b/drivers/mmc/host/cavium-octeon.c > @@ -217,7 +217,7 @@ static int octeon_mmc_probe(struct platform_device *pdev) > return PTR_ERR(base); > host->dma_base = base; > /* > - * To keep the register addresses shared we intentionaly use > + * To keep the register addresses shared we intentionally use > * a negative offset here, first register used on Octeon therefore > * starts at 0x20 (MIO_EMM_DMA_CFG). > */ > diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c > index 41e451235f63..aab1a8df6414 100644 > --- a/drivers/mmc/host/dw_mmc.c > +++ b/drivers/mmc/host/dw_mmc.c > @@ -1182,7 +1182,7 @@ static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) > /* > * Use the initial fifoth_val for PIO mode. If wm_algined > * is set, we set watermark same as data size. > - * If next issued data may be transfered by DMA mode, > + * If next issued data may be transferred by DMA mode, > * prev_blksz should be invalidated. > */ > if (host->wm_aligned) > diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c > index c7c067b9415a..e87d1c4b9dc1 100644 > --- a/drivers/mmc/host/meson-gx-mmc.c > +++ b/drivers/mmc/host/meson-gx-mmc.c > @@ -879,7 +879,7 @@ static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) > /* > * The memory at the end of the controller used as bounce buffer for > * the dram_access_quirk only accepts 32bit read/write access, > - * check the aligment and length of the data before starting the request. > + * check the alignment and length of the data before starting the request. > */ > if (host->dram_access_quirk && mrq->data) { > mrq->cmd->error = meson_mmc_validate_dram_access(mmc, mrq->data); > diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h > index a5eb4ced4d5d..4d3647f9ec06 100644 > --- a/drivers/mmc/host/mmci.h > +++ b/drivers/mmc/host/mmci.h > @@ -77,7 +77,7 @@ > #define MCI_CPSM_INTERRUPT BIT(8) > #define MCI_CPSM_PENDING BIT(9) > #define MCI_CPSM_ENABLE BIT(10) > -/* Command register flag extenstions in the ST Micro versions */ > +/* Command register flag extensions in the ST Micro versions */ > #define MCI_CPSM_ST_SDIO_SUSP BIT(11) > #define MCI_CPSM_ST_ENCMD_COMPL BIT(12) > #define MCI_CPSM_ST_NIEN BIT(13) > diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c > index 8f0bc6dca2b0..2bfb86364441 100644 > --- a/drivers/mmc/host/sdhci-esdhc-imx.c > +++ b/drivers/mmc/host/sdhci-esdhc-imx.c > @@ -1524,7 +1524,7 @@ static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) > writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); > } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { > /* > - * ESDHC_STD_TUNING_EN may be configed in bootloader > + * ESDHC_STD_TUNING_EN may be configured in bootloader > * or ROM code, so clear this bit here to make sure > * the manual tuning can work. > */ > @@ -1626,7 +1626,7 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, > > /* > * If we have this property, then activate WP check. > - * Retrieveing and requesting the actual WP GPIO will happen > + * Retrieving and requesting the actual WP GPIO will happen > * in the call to mmc_of_parse(). > */ > if (of_property_read_bool(np, "wp-gpios")) > diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c > index e113b99a3eab..d6b3b343b031 100644 > --- a/drivers/mmc/host/sdhci-msm.c > +++ b/drivers/mmc/host/sdhci-msm.c > @@ -2601,7 +2601,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) > sdhci_msm_handle_pwr_irq(host, 0); > > /* > - * Ensure that above writes are propogated before interrupt enablement > + * Ensure that above writes are propagated before interrupt enablement > * in GIC. > */ > mb(); > -- > 2.34.1 >
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c index 6490df54a6f5..f444ca5dd154 100644 --- a/drivers/mmc/host/atmel-mci.c +++ b/drivers/mmc/host/atmel-mci.c @@ -860,7 +860,7 @@ static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) } /* - * Configure given PDC buffer taking care of alignement issues. + * Configure given PDC buffer taking care of alignment issues. * Update host->data_size and host->sg. */ static void atmci_pdc_set_single_buf(struct atmel_mci *host, diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c index 6e80bcb668ec..7393d2ea5e57 100644 --- a/drivers/mmc/host/au1xmmc.c +++ b/drivers/mmc/host/au1xmmc.c @@ -543,7 +543,7 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24; } } else { - /* Techincally, we should be getting all 48 bits of + /* Technically, we should be getting all 48 bits of * the response (SD_RESP1 + SD_RESP2), but because * our response omits the CRC, our data ends up * being shifted 8 bits to the right. In this case, diff --git a/drivers/mmc/host/cavium-octeon.c b/drivers/mmc/host/cavium-octeon.c index 060ec4f4800f..d150d83b41ed 100644 --- a/drivers/mmc/host/cavium-octeon.c +++ b/drivers/mmc/host/cavium-octeon.c @@ -217,7 +217,7 @@ static int octeon_mmc_probe(struct platform_device *pdev) return PTR_ERR(base); host->dma_base = base; /* - * To keep the register addresses shared we intentionaly use + * To keep the register addresses shared we intentionally use * a negative offset here, first register used on Octeon therefore * starts at 0x20 (MIO_EMM_DMA_CFG). */ diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 41e451235f63..aab1a8df6414 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -1182,7 +1182,7 @@ static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) /* * Use the initial fifoth_val for PIO mode. If wm_algined * is set, we set watermark same as data size. - * If next issued data may be transfered by DMA mode, + * If next issued data may be transferred by DMA mode, * prev_blksz should be invalidated. */ if (host->wm_aligned) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index c7c067b9415a..e87d1c4b9dc1 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -879,7 +879,7 @@ static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) /* * The memory at the end of the controller used as bounce buffer for * the dram_access_quirk only accepts 32bit read/write access, - * check the aligment and length of the data before starting the request. + * check the alignment and length of the data before starting the request. */ if (host->dram_access_quirk && mrq->data) { mrq->cmd->error = meson_mmc_validate_dram_access(mmc, mrq->data); diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index a5eb4ced4d5d..4d3647f9ec06 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -77,7 +77,7 @@ #define MCI_CPSM_INTERRUPT BIT(8) #define MCI_CPSM_PENDING BIT(9) #define MCI_CPSM_ENABLE BIT(10) -/* Command register flag extenstions in the ST Micro versions */ +/* Command register flag extensions in the ST Micro versions */ #define MCI_CPSM_ST_SDIO_SUSP BIT(11) #define MCI_CPSM_ST_ENCMD_COMPL BIT(12) #define MCI_CPSM_ST_NIEN BIT(13) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 8f0bc6dca2b0..2bfb86364441 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -1524,7 +1524,7 @@ static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { /* - * ESDHC_STD_TUNING_EN may be configed in bootloader + * ESDHC_STD_TUNING_EN may be configured in bootloader * or ROM code, so clear this bit here to make sure * the manual tuning can work. */ @@ -1626,7 +1626,7 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, /* * If we have this property, then activate WP check. - * Retrieveing and requesting the actual WP GPIO will happen + * Retrieving and requesting the actual WP GPIO will happen * in the call to mmc_of_parse(). */ if (of_property_read_bool(np, "wp-gpios")) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index e113b99a3eab..d6b3b343b031 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -2601,7 +2601,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) sdhci_msm_handle_pwr_irq(host, 0); /* - * Ensure that above writes are propogated before interrupt enablement + * Ensure that above writes are propagated before interrupt enablement * in GIC. */ mb();
This patch corrects several typos in comments within the mmc/host directory. No functional changes are introduced, only comment improvements for better readability. Detected using codespell. Signed-off-by: Yu Jiaoliang <yujiaoliang@vivo.com> --- drivers/mmc/host/atmel-mci.c | 2 +- drivers/mmc/host/au1xmmc.c | 2 +- drivers/mmc/host/cavium-octeon.c | 2 +- drivers/mmc/host/dw_mmc.c | 2 +- drivers/mmc/host/meson-gx-mmc.c | 2 +- drivers/mmc/host/mmci.h | 2 +- drivers/mmc/host/sdhci-esdhc-imx.c | 4 ++-- drivers/mmc/host/sdhci-msm.c | 2 +- 8 files changed, 9 insertions(+), 9 deletions(-)