Message ID | 20240822152801.602318-7-claudiu.beznea.uj@bp.renesas.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Geert Uytterhoeven |
Headers | show |
Series | Add initial USB support for the Renesas RZ/G3S SoC | expand |
On Thu, Aug 22, 2024 at 06:27:51PM +0300, Claudiu wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Document the Renesas RZ/G3S USB PHY Control IP. This is similar with the > one found on the RZ/G2L SoC the exception being that the SYSC USB specific > signal need to be configured before accessing the USB area. This is > done though a reset signal. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Hi Claudiu, On Thu, Aug 22, 2024 at 5:28 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Document the Renesas RZ/G3S USB PHY Control IP. This is similar with the > one found on the RZ/G2L SoC the exception being that the SYSC USB specific > signal need to be configured before accessing the USB area. This is > done though a reset signal. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Thanks for your patch! > --- a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml > +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml > @@ -15,12 +15,15 @@ description: > > properties: > compatible: > - items: > - - enum: > - - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five > - - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} > - - renesas,r9a07g054-usbphy-ctrl # RZ/V2L > - - const: renesas,rzg2l-usbphy-ctrl > + oneOf: > + - const: renesas,r9a08g045-usbphy-ctrl # RZ/G3S > + Unneeded blank line. > + - items: > + - enum: > + - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five > + - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} > + - renesas,r9a07g054-usbphy-ctrl # RZ/V2L > + - const: renesas,rzg2l-usbphy-ctrl Nit: usually these are sorted by part number, so the RZ/G3S section should be last. For the contents: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml index b0b20af15313..5f053981474e 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml @@ -15,12 +15,15 @@ description: properties: compatible: - items: - - enum: - - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five - - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} - - renesas,r9a07g054-usbphy-ctrl # RZ/V2L - - const: renesas,rzg2l-usbphy-ctrl + oneOf: + - const: renesas,r9a08g045-usbphy-ctrl # RZ/G3S + + - items: + - enum: + - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five + - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} + - renesas,r9a07g054-usbphy-ctrl # RZ/V2L + - const: renesas,rzg2l-usbphy-ctrl reg: maxItems: 1 @@ -29,7 +32,8 @@ properties: maxItems: 1 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 power-domains: maxItems: 1 @@ -59,6 +63,23 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a08g045-usbphy-ctrl + then: + properties: + resets: + items: + - description: USB PHY Control module reset + - description: USB area reset + else: + properties: + resets: + maxItems: 1 + examples: - | #include <dt-bindings/clock/r9a07g044-cpg.h>