| Message ID | 20241008223741.82790-6-matthew.s.atwood@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add xe3lpd edp enabling | expand |
On Tue, Oct 08, 2024 at 03:37:36PM -0700, Matt Atwood wrote: > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > Xe3_LPD has new max cdclk of 691200 which requires reusing the lnl table > and modify/add higher frequencies. Updating the max cdclk supported by > the platform and voltage_level determination is also updated. > > There are minor changes in cdclk programming sequence compared to lnl, > where programming cd2x divider needs to be skipped. This is already handled > by the calculations in existing code. > > Bspec: 68861, 68863, 68864 > Cc: Gustavo Sousa <gustavo.sousa@intel.com> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 56 +++++++++++++++++++++- > 1 file changed, 54 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index fa1c2012b10c..6ac7bd6afc36 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -1468,6 +1468,32 @@ static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { > {} > }; > > +static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = { > + { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, > + { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, > + { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, > + { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, > + { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, > + { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, Up to this point the table seems to match what I see in the spec. But after this point most of the entries below don't show up in the bspec, and the ones in the bspec aren't included here. Looks like things have changed since this patch was originally written. > + { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 }, > + { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee }, > + { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de }, > + { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe }, > + { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe }, > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe }, > + { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe }, > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 561600, .ratio = 36, .waveform = 0xf7de }, > + { .refclk = 38400, .cdclk = 604800, .ratio = 36, .waveform = 0xfefe }, > + { .refclk = 38400, .cdclk = 648000, .ratio = 36, .waveform = 0xfffe }, > + { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, > + {} > +}; > + > static const int cdclk_squash_len = 16; > > static int cdclk_squash_divider(u16 waveform) > @@ -1594,6 +1620,20 @@ static u8 rplu_calc_voltage_level(int cdclk) > rplu_voltage_level_max_cdclk); > } > > +static u8 xe3lpd_calc_voltage_level(int cdclk) > +{ > + static const int xe3lpd_voltage_level_max_cdclk[] = { > + [0] = 307200, > + [1] = 480000, > + [2] = 556800, > + [3] = 691200, > + }; This doesn't seem to match the spec either. I only see two levels (vmin and elevated) rather than four. Matt > + > + return calc_voltage_level(cdclk, > + ARRAY_SIZE(xe3lpd_voltage_level_max_cdclk), > + xe3lpd_voltage_level_max_cdclk); > +} > + > static void icl_readout_refclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > @@ -3437,7 +3477,9 @@ void intel_update_max_cdclk(struct intel_display *display) > { > struct drm_i915_private *dev_priv = to_i915(display->drm); > > - if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { > + if (DISPLAY_VER(display) >= 30) { > + display->cdclk.max_cdclk_freq = 691200; > + } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { > if (display->cdclk.hw.ref == 24000) > display->cdclk.max_cdclk_freq = 552000; > else > @@ -3650,6 +3692,13 @@ void intel_cdclk_debugfs_register(struct intel_display *display) > display, &i915_cdclk_info_fops); > } > > +static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = { > + .get_cdclk = bxt_get_cdclk, > + .set_cdclk = bxt_set_cdclk, > + .modeset_calc_cdclk = bxt_modeset_calc_cdclk, > + .calc_voltage_level = xe3lpd_calc_voltage_level, > +}; > + > static const struct intel_cdclk_funcs rplu_cdclk_funcs = { > .get_cdclk = bxt_get_cdclk, > .set_cdclk = bxt_set_cdclk, > @@ -3794,7 +3843,10 @@ void intel_init_cdclk_hooks(struct intel_display *display) > { > struct drm_i915_private *dev_priv = to_i915(display->drm); > > - if (DISPLAY_VER(display) >= 20) { > + if (DISPLAY_VER(display) >= 30) { > + display->funcs.cdclk = &xe3lpd_cdclk_funcs; > + display->cdclk.table = xe3lpd_cdclk_table; > + } else if (DISPLAY_VER(display) >= 20) { > display->funcs.cdclk = &rplu_cdclk_funcs; > display->cdclk.table = xe2lpd_cdclk_table; > } else if (DISPLAY_VER_FULL(display) >= IP_VER(14, 1)) { > -- > 2.45.0 >
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index fa1c2012b10c..6ac7bd6afc36 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1468,6 +1468,32 @@ static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { {} }; +static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = { + { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, + { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, + { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, + { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, + { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, + { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, + { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 }, + { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee }, + { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de }, + { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe }, + { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe }, + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, + { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe }, + { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe }, + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, + { .refclk = 38400, .cdclk = 561600, .ratio = 36, .waveform = 0xf7de }, + { .refclk = 38400, .cdclk = 604800, .ratio = 36, .waveform = 0xfefe }, + { .refclk = 38400, .cdclk = 648000, .ratio = 36, .waveform = 0xfffe }, + { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, + {} +}; + static const int cdclk_squash_len = 16; static int cdclk_squash_divider(u16 waveform) @@ -1594,6 +1620,20 @@ static u8 rplu_calc_voltage_level(int cdclk) rplu_voltage_level_max_cdclk); } +static u8 xe3lpd_calc_voltage_level(int cdclk) +{ + static const int xe3lpd_voltage_level_max_cdclk[] = { + [0] = 307200, + [1] = 480000, + [2] = 556800, + [3] = 691200, + }; + + return calc_voltage_level(cdclk, + ARRAY_SIZE(xe3lpd_voltage_level_max_cdclk), + xe3lpd_voltage_level_max_cdclk); +} + static void icl_readout_refclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { @@ -3437,7 +3477,9 @@ void intel_update_max_cdclk(struct intel_display *display) { struct drm_i915_private *dev_priv = to_i915(display->drm); - if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { + if (DISPLAY_VER(display) >= 30) { + display->cdclk.max_cdclk_freq = 691200; + } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { if (display->cdclk.hw.ref == 24000) display->cdclk.max_cdclk_freq = 552000; else @@ -3650,6 +3692,13 @@ void intel_cdclk_debugfs_register(struct intel_display *display) display, &i915_cdclk_info_fops); } +static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = { + .get_cdclk = bxt_get_cdclk, + .set_cdclk = bxt_set_cdclk, + .modeset_calc_cdclk = bxt_modeset_calc_cdclk, + .calc_voltage_level = xe3lpd_calc_voltage_level, +}; + static const struct intel_cdclk_funcs rplu_cdclk_funcs = { .get_cdclk = bxt_get_cdclk, .set_cdclk = bxt_set_cdclk, @@ -3794,7 +3843,10 @@ void intel_init_cdclk_hooks(struct intel_display *display) { struct drm_i915_private *dev_priv = to_i915(display->drm); - if (DISPLAY_VER(display) >= 20) { + if (DISPLAY_VER(display) >= 30) { + display->funcs.cdclk = &xe3lpd_cdclk_funcs; + display->cdclk.table = xe3lpd_cdclk_table; + } else if (DISPLAY_VER(display) >= 20) { display->funcs.cdclk = &rplu_cdclk_funcs; display->cdclk.table = xe2lpd_cdclk_table; } else if (DISPLAY_VER_FULL(display) >= IP_VER(14, 1)) {