| Message ID | 20241008070708.1985805-3-wei.fang@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | make PHY output RMII reference clock | expand |
On Tue, Oct 08, 2024 at 03:07:08PM +0800, Wei Fang wrote: > @@ -1561,8 +1565,13 @@ static int nxp_c45_set_phy_mode(struct phy_device *phydev) > phydev_err(phydev, "rmii mode not supported\n"); > return -EINVAL; > } > - phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, > - MII_BASIC_CONFIG_RMII); > + > + if (priv->flags & TJA11XX_REVERSE_MODE) > + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, > + MII_BASIC_CONFIG_RMII | MII_BASIC_CONFIG_REV); > + else > + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, > + MII_BASIC_CONFIG_RMII); Netdev has an 80 column limit, and this needs commenting because we have PHY_INTERFACE_MODE_REVRMII which could be confused with this (although I haven't checked.) u16 basic_config; ... basic_config = MII_BASIC_CONFIG_RMII; /* This is not PHY_INTERFACE_MODE_REVRMII */ if (priv->flags & TJA11XX_REVERSE_MODE) basic_config |= MII_BASIC_CONFIG_REV; phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, basic_config); is much nicer to read. Thanks.
> -----Original Message----- > From: Russell King <linux@armlinux.org.uk> > Sent: 2024年10月8日 16:31 > To: Wei Fang <wei.fang@nxp.com> > Cc: davem@davemloft.net; edumazet@google.com; kuba@kernel.org; > pabeni@redhat.com; robh@kernel.org; krzk+dt@kernel.org; > conor+dt@kernel.org; andrew@lunn.ch; f.fainelli@gmail.com; > hkallweit1@gmail.com; Andrei Botila (OSS) <andrei.botila@oss.nxp.com>; > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > netdev@vger.kernel.org; imx@lists.linux.dev > Subject: Re: [PATCH v2 net-next 2/2] net: phy: c45-tja11xx: add support for > outputing RMII reference clock > > On Tue, Oct 08, 2024 at 03:07:08PM +0800, Wei Fang wrote: > > @@ -1561,8 +1565,13 @@ static int nxp_c45_set_phy_mode(struct > phy_device *phydev) > > phydev_err(phydev, "rmii mode not supported\n"); > > return -EINVAL; > > } > > - phy_write_mmd(phydev, MDIO_MMD_VEND1, > VEND1_MII_BASIC_CONFIG, > > - MII_BASIC_CONFIG_RMII); > > + > > + if (priv->flags & TJA11XX_REVERSE_MODE) > > + phy_write_mmd(phydev, MDIO_MMD_VEND1, > VEND1_MII_BASIC_CONFIG, > > + MII_BASIC_CONFIG_RMII | > MII_BASIC_CONFIG_REV); > > + else > > + phy_write_mmd(phydev, MDIO_MMD_VEND1, > VEND1_MII_BASIC_CONFIG, > > + MII_BASIC_CONFIG_RMII); > > Netdev has an 80 column limit, and this needs commenting because we have > PHY_INTERFACE_MODE_REVRMII which could be confused with this (although > I haven't checked.) > > u16 basic_config; > ... > basic_config = MII_BASIC_CONFIG_RMII; > > /* This is not PHY_INTERFACE_MODE_REVRMII */ > if (priv->flags & TJA11XX_REVERSE_MODE) > basic_config |= MII_BASIC_CONFIG_REV; > > phy_write_mmd(phydev, MDIO_MMD_VEND1, > VEND1_MII_BASIC_CONFIG, > basic_config); > > is much nicer to read. > Okay, I will refine the patch, thanks!
On Tue, Oct 08, 2024 at 03:07:08PM +0800, Wei Fang wrote: > For TJA11xx PHYs, they have the capability to output 50MHz reference > clock on REF_CLK pin in RMII mode, which is called "revRMII" mode in > the PHY data sheet. > > Signed-off-by: Wei Fang <wei.fang@nxp.com> Hi, As it looks like there will be a v3 anyway, please consider correcting the spelling of outputting in the subject. Thanks!
> -----Original Message----- > From: Simon Horman <horms@kernel.org> > Sent: 2024年10月9日 19:58 > To: Wei Fang <wei.fang@nxp.com> > Cc: davem@davemloft.net; edumazet@google.com; kuba@kernel.org; > pabeni@redhat.com; robh@kernel.org; krzk+dt@kernel.org; > conor+dt@kernel.org; andrew@lunn.ch; f.fainelli@gmail.com; > hkallweit1@gmail.com; Andrei Botila (OSS) <andrei.botila@oss.nxp.com>; > linux@armlinux.org.uk; devicetree@vger.kernel.org; > linux-kernel@vger.kernel.org; netdev@vger.kernel.org; imx@lists.linux.dev > Subject: Re: [PATCH v2 net-next 2/2] net: phy: c45-tja11xx: add support for > outputing RMII reference clock > > On Tue, Oct 08, 2024 at 03:07:08PM +0800, Wei Fang wrote: > > For TJA11xx PHYs, they have the capability to output 50MHz reference > > clock on REF_CLK pin in RMII mode, which is called "revRMII" mode in > > the PHY data sheet. > > > > Signed-off-by: Wei Fang <wei.fang@nxp.com> > > Hi, > > As it looks like there will be a v3 anyway, > please consider correcting the spelling of outputting in the subject. > > Thanks! Thanks for pointing this typo, I will correct it in next version.
diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c index 5af5ade4fc64..3fe630a72ff1 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.c +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -10,6 +10,7 @@ #include <linux/kernel.h> #include <linux/mii.h> #include <linux/module.h> +#include <linux/of.h> #include <linux/phy.h> #include <linux/processor.h> #include <linux/property.h> @@ -185,6 +186,8 @@ #define NXP_C45_SKB_CB(skb) ((struct nxp_c45_skb_cb *)(skb)->cb) +#define TJA11XX_REVERSE_MODE BIT(0) + struct nxp_c45_phy; struct nxp_c45_skb_cb { @@ -1510,6 +1513,7 @@ static int nxp_c45_get_delays(struct phy_device *phydev) static int nxp_c45_set_phy_mode(struct phy_device *phydev) { + struct nxp_c45_phy *priv = phydev->priv; int ret; ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_ABILITIES); @@ -1561,8 +1565,13 @@ static int nxp_c45_set_phy_mode(struct phy_device *phydev) phydev_err(phydev, "rmii mode not supported\n"); return -EINVAL; } - phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, - MII_BASIC_CONFIG_RMII); + + if (priv->flags & TJA11XX_REVERSE_MODE) + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, + MII_BASIC_CONFIG_RMII | MII_BASIC_CONFIG_REV); + else + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, + MII_BASIC_CONFIG_RMII); break; case PHY_INTERFACE_MODE_SGMII: if (!(ret & SGMII_ABILITY)) { @@ -1623,6 +1632,20 @@ static int nxp_c45_get_features(struct phy_device *phydev) return genphy_c45_pma_read_abilities(phydev); } +static int nxp_c45_parse_dt(struct phy_device *phydev) +{ + struct device_node *node = phydev->mdio.dev.of_node; + struct nxp_c45_phy *priv = phydev->priv; + + if (!IS_ENABLED(CONFIG_OF_MDIO)) + return 0; + + if (of_property_read_bool(node, "nxp,rmii-refclk-out")) + priv->flags |= TJA11XX_REVERSE_MODE; + + return 0; +} + static int nxp_c45_probe(struct phy_device *phydev) { struct nxp_c45_phy *priv; @@ -1642,6 +1665,8 @@ static int nxp_c45_probe(struct phy_device *phydev) phydev->priv = priv; + nxp_c45_parse_dt(phydev); + mutex_init(&priv->ptp_lock); phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1, diff --git a/drivers/net/phy/nxp-c45-tja11xx.h b/drivers/net/phy/nxp-c45-tja11xx.h index f364fca68f0b..8b5fc383752b 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.h +++ b/drivers/net/phy/nxp-c45-tja11xx.h @@ -28,6 +28,7 @@ struct nxp_c45_phy { int extts_index; bool extts; struct nxp_c45_macsec *macsec; + u32 flags; }; #if IS_ENABLED(CONFIG_MACSEC)
For TJA11xx PHYs, they have the capability to output 50MHz reference clock on REF_CLK pin in RMII mode, which is called "revRMII" mode in the PHY data sheet. Signed-off-by: Wei Fang <wei.fang@nxp.com> --- V2 changes: 1. Change the property name. 2. Modify the subject and commit message. V3 changes: No changes. V4 changes: 1. Change the property name based on patch 1. --- drivers/net/phy/nxp-c45-tja11xx.c | 29 +++++++++++++++++++++++++++-- drivers/net/phy/nxp-c45-tja11xx.h | 1 + 2 files changed, 28 insertions(+), 2 deletions(-)