| Message ID | 20240930145244.356565-2-fabrizio.castro.jz@renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add support for the RZ/V2H Interrupt Control Unit | expand |
On Mon, Sep 30, 2024 at 4:53 PM Fabrizio Castro <fabrizio.castro.jz@renesas.com> wrote: > The RZ/V2H(P) has 16 IRQ interrupts, while every other platforms > has 8, and this affects the start index of TINT interrupts > (1 + 16 = 17, rather than 1 + 8 = 9). > Macro RZG2L_TINT_IRQ_START_INDEX cannot work anymore, replace > it with a new member within struct rzg2l_hwcfg. > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > --- > v1->v2: > * No change Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-pinctrl for v6.13. Gr{oetje,eeting}s, Geert
On 30.09.2024 17:52, Fabrizio Castro wrote: > The RZ/V2H(P) has 16 IRQ interrupts, while every other platforms > has 8, and this affects the start index of TINT interrupts > (1 + 16 = 17, rather than 1 + 8 = 9). > Macro RZG2L_TINT_IRQ_START_INDEX cannot work anymore, replace > it with a new member within struct rzg2l_hwcfg. > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > v1->v2: > * No change > > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > index 5a403915fed2..0aba75dce229 100644 > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -168,7 +168,6 @@ > #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) > > #define RZG2L_TINT_MAX_INTERRUPT 32 > -#define RZG2L_TINT_IRQ_START_INDEX 9 > #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) > > /* Custom pinconf parameters */ > @@ -251,6 +250,7 @@ enum rzg2l_iolh_index { > * @func_base: base number for port function (see register PFC) > * @oen_max_pin: the maximum pin number supporting output enable > * @oen_max_port: the maximum port number supporting output enable > + * @tint_start_index: the start index for the TINT interrupts > */ > struct rzg2l_hwcfg { > const struct rzg2l_register_offsets regs; > @@ -262,6 +262,7 @@ struct rzg2l_hwcfg { > u8 func_base; > u8 oen_max_pin; > u8 oen_max_port; > + unsigned int tint_start_index; Maybe you can use u16 (even u8 is enough at the moment) and add it a bit above (if u16 or even if unsigned int) to avoid any padding, if any. > }; > > struct rzg2l_dedicated_configs { > @@ -2379,7 +2380,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, > > rzg2l_gpio_irq_endisable(pctrl, child, true); > pctrl->hwirq[irq] = child; > - irq += RZG2L_TINT_IRQ_START_INDEX; > + irq += pctrl->data->hwcfg->tint_start_index; > > /* All these interrupts are level high in the CPU */ > *parent_type = IRQ_TYPE_LEVEL_HIGH; > @@ -3035,6 +3036,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { > }, > .iolh_groupb_oi = { 100, 66, 50, 33, }, > .oen_max_pin = 0, > + .tint_start_index = 9, > }; > > static const struct rzg2l_hwcfg rzg3s_hwcfg = { > @@ -3067,12 +3069,14 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = { > .func_base = 1, > .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */ > .oen_max_port = 7, /* P7_1 is the maximum OEN port. */ > + .tint_start_index = 9, > }; > > static const struct rzg2l_hwcfg rzv2h_hwcfg = { > .regs = { > .pwpr = 0x3c04, > }, > + .tint_start_index = 17, > }; > > static struct rzg2l_pinctrl_data r9a07g043_data = {
Hi Claudiu, On Wed, Oct 9, 2024 at 10:00 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote: > On 30.09.2024 17:52, Fabrizio Castro wrote: > > The RZ/V2H(P) has 16 IRQ interrupts, while every other platforms > > has 8, and this affects the start index of TINT interrupts > > (1 + 16 = 17, rather than 1 + 8 = 9). > > Macro RZG2L_TINT_IRQ_START_INDEX cannot work anymore, replace > > it with a new member within struct rzg2l_hwcfg. > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > > Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Thanks! > > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > > @@ -251,6 +250,7 @@ enum rzg2l_iolh_index { > > * @func_base: base number for port function (see register PFC) > > * @oen_max_pin: the maximum pin number supporting output enable > > * @oen_max_port: the maximum port number supporting output enable > > + * @tint_start_index: the start index for the TINT interrupts > > */ > > struct rzg2l_hwcfg { > > const struct rzg2l_register_offsets regs; > > @@ -262,6 +262,7 @@ struct rzg2l_hwcfg { > > u8 func_base; > > u8 oen_max_pin; > > u8 oen_max_port; > > + unsigned int tint_start_index; > > Maybe you can use u16 (even u8 is enough at the moment) and add it a bit > above (if u16 or even if unsigned int) to avoid any padding, if any. Good catch, I had missed that struct rzg2l_register_offsets is 16-bit aligned ;-) I will change it to u16 and move it up while applying. Gr{oetje,eeting}s, Geert
Hi Geert, hi Claudiu, Thanks for your feedback! > From: Geert Uytterhoeven <geert@linux-m68k.org> > Sent: Wednesday, October 9, 2024 11:23 AM > To: Claudiu.Beznea <claudiu.beznea@tuxon.dev> > Cc: Fabrizio Castro <fabrizio.castro.jz@renesas.com>; Linus Walleij <linus.walleij@linaro.org>; Geert > Uytterhoeven <geert+renesas@glider.be>; linux-renesas-soc@vger.kernel.org; linux-gpio@vger.kernel.org; > linux-kernel@vger.kernel.org; Chris Paterson <Chris.Paterson2@renesas.com>; Biju Das > <biju.das.jz@bp.renesas.com>; Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> > Subject: Re: [PATCH v2 1/5] pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX > > Hi Claudiu, > > On Wed, Oct 9, 2024 at 10:00 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote: > > On 30.09.2024 17:52, Fabrizio Castro wrote: > > > The RZ/V2H(P) has 16 IRQ interrupts, while every other platforms > > > has 8, and this affects the start index of TINT interrupts > > > (1 + 16 = 17, rather than 1 + 8 = 9). > > > Macro RZG2L_TINT_IRQ_START_INDEX cannot work anymore, replace > > > it with a new member within struct rzg2l_hwcfg. > > > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > > > > Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Thanks! > > > > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > > > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > > > > @@ -251,6 +250,7 @@ enum rzg2l_iolh_index { > > > * @func_base: base number for port function (see register PFC) > > > * @oen_max_pin: the maximum pin number supporting output enable > > > * @oen_max_port: the maximum port number supporting output enable > > > + * @tint_start_index: the start index for the TINT interrupts > > > */ > > > struct rzg2l_hwcfg { > > > const struct rzg2l_register_offsets regs; > > > @@ -262,6 +262,7 @@ struct rzg2l_hwcfg { > > > u8 func_base; > > > u8 oen_max_pin; > > > u8 oen_max_port; > > > + unsigned int tint_start_index; > > > > Maybe you can use u16 (even u8 is enough at the moment) and add it a bit > > above (if u16 or even if unsigned int) to avoid any padding, if any. > > Good catch, I had missed that struct rzg2l_register_offsets is 16-bit > aligned ;-) > > I will change it to u16 and move it up while applying. Thank you both. Kind regards, Fab > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 5a403915fed2..0aba75dce229 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -168,7 +168,6 @@ #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) #define RZG2L_TINT_MAX_INTERRUPT 32 -#define RZG2L_TINT_IRQ_START_INDEX 9 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) /* Custom pinconf parameters */ @@ -251,6 +250,7 @@ enum rzg2l_iolh_index { * @func_base: base number for port function (see register PFC) * @oen_max_pin: the maximum pin number supporting output enable * @oen_max_port: the maximum port number supporting output enable + * @tint_start_index: the start index for the TINT interrupts */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; @@ -262,6 +262,7 @@ struct rzg2l_hwcfg { u8 func_base; u8 oen_max_pin; u8 oen_max_port; + unsigned int tint_start_index; }; struct rzg2l_dedicated_configs { @@ -2379,7 +2380,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, rzg2l_gpio_irq_endisable(pctrl, child, true); pctrl->hwirq[irq] = child; - irq += RZG2L_TINT_IRQ_START_INDEX; + irq += pctrl->data->hwcfg->tint_start_index; /* All these interrupts are level high in the CPU */ *parent_type = IRQ_TYPE_LEVEL_HIGH; @@ -3035,6 +3036,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { }, .iolh_groupb_oi = { 100, 66, 50, 33, }, .oen_max_pin = 0, + .tint_start_index = 9, }; static const struct rzg2l_hwcfg rzg3s_hwcfg = { @@ -3067,12 +3069,14 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = { .func_base = 1, .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */ .oen_max_port = 7, /* P7_1 is the maximum OEN port. */ + .tint_start_index = 9, }; static const struct rzg2l_hwcfg rzv2h_hwcfg = { .regs = { .pwpr = 0x3c04, }, + .tint_start_index = 17, }; static struct rzg2l_pinctrl_data r9a07g043_data = {
The RZ/V2H(P) has 16 IRQ interrupts, while every other platforms has 8, and this affects the start index of TINT interrupts (1 + 16 = 17, rather than 1 + 8 = 9). Macro RZG2L_TINT_IRQ_START_INDEX cannot work anymore, replace it with a new member within struct rzg2l_hwcfg. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> --- v1->v2: * No change drivers/pinctrl/renesas/pinctrl-rzg2l.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)