| Message ID | 20241010144845.2555983-1-s-vadapalli@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | phy: ti: gmii-sel: Enable USXGMII mode for J7200 | expand |
On 10/10/2024 17:48, Siddharth Vadapalli wrote: > TI's J7200 SoC supports USXGMII mode with the CPSW5G instance's MAC Port1. > Add USXGMII mode to the extra_modes member of J7200's SoC data. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org>
On Thu, 10 Oct 2024 20:18:45 +0530, Siddharth Vadapalli wrote: > TI's J7200 SoC supports USXGMII mode with the CPSW5G instance's MAC Port1. > Add USXGMII mode to the extra_modes member of J7200's SoC data. > > Applied, thanks! [1/1] phy: ti: gmii-sel: Enable USXGMII mode for J7200 commit: 9e544d46a2d11a0cb8b30d8ad4409c59bc168ce2 Best regards,
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index 103b266fec77..e0ca59ae3153 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -230,7 +230,8 @@ static const struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = { .use_of_data = true, .regfields = phy_gmii_sel_fields_am654, - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | + BIT(PHY_INTERFACE_MODE_USXGMII), .num_ports = 4, .num_qsgmii_main_ports = 1, };
TI's J7200 SoC supports USXGMII mode with the CPSW5G instance's MAC Port1. Add USXGMII mode to the extra_modes member of J7200's SoC data. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> --- Hello, This patch is based on linux-next tagged next-20241010. Regards, Siddharth. drivers/phy/ti/phy-gmii-sel.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)