diff mbox series

[v4,2/4] x86/mce: Remove functions that disable error reporting

Message ID 20240923073311.4290-3-TonyWWang-oc@zhaoxin.com (mailing list archive)
State New
Headers show
Series x86/mce: Add Zhaoxin MCE support and remove | expand

Commit Message

Tony W Wang-oc Sept. 23, 2024, 7:33 a.m. UTC 
From: Lyle Li <LyleLi@zhaoxin.com>

Since all major vendors do not disable MCA_CTL after initialization,
functions that disable error reporting should be removed in mce/core.c.

Signed-off-by: Lyle Li <LyleLi@zhaoxin.com>
Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
---
 arch/x86/kernel/cpu/mce/core.c | 50 ----------------------------------
 1 file changed, 50 deletions(-)

Comments

Zhuo, Qiuxu Oct. 12, 2024, 5:37 a.m. UTC | #1 
> From: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
> [...]
> Subject: [PATCH v4 2/4] x86/mce: Remove functions that disable error reporting
> 
> From: Lyle Li <LyleLi@zhaoxin.com>
> 
> Since all major vendors do not disable MCA_CTL after initialization, functions
> that disable error reporting should be removed in mce/core.c.

It's obvious from this patch that the functions are removed from mce/core.c. 
IMHO: No need to mention the file name in the commit message.

And please use active voice in the commit message, like this:

    Since all major vendors do not disable MCA_CTL after initialization, remove the functions that disable error reporting.

Other than that:

    Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>

> [...]
diff mbox series

Patch

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 4ad6b5083..1654133da 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -2376,53 +2376,6 @@  int __init mcheck_init(void)
  * mce_syscore: PM support
  */
 
-/*
- * Disable machine checks on suspend and shutdown. We can't really handle
- * them later.
- */
-static void mce_disable_error_reporting(void)
-{
-	struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
-	int i;
-
-	for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
-		struct mce_bank *b = &mce_banks[i];
-
-		if (b->init)
-			wrmsrl(mca_msr_reg(i, MCA_CTL), 0);
-	}
-	return;
-}
-
-static void vendor_disable_error_reporting(void)
-{
-	/*
-	 * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
-	 * MSRs are socket-wide. Disabling them for just a single offlined CPU
-	 * is bad, since it will inhibit reporting for all shared resources on
-	 * the socket like the last level cache (LLC), the integrated memory
-	 * controller (iMC), etc.
-	 */
-	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
-	    boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
-	    boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
-	    boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
-		return;
-
-	mce_disable_error_reporting();
-}
-
-static int mce_syscore_suspend(void)
-{
-	vendor_disable_error_reporting();
-	return 0;
-}
-
-static void mce_syscore_shutdown(void)
-{
-	vendor_disable_error_reporting();
-}
-
 /*
  * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
  * Only one CPU is active at this time, the others get re-added later using
@@ -2436,8 +2389,6 @@  static void mce_syscore_resume(void)
 }
 
 static struct syscore_ops mce_syscore_ops = {
-	.suspend	= mce_syscore_suspend,
-	.shutdown	= mce_syscore_shutdown,
 	.resume		= mce_syscore_resume,
 };
 
@@ -2722,7 +2673,6 @@  static void mce_disable_cpu(void)
 	if (!cpuhp_tasks_frozen)
 		cmci_clear();
 
-	vendor_disable_error_reporting();
 }
 
 static void mce_reenable_cpu(void)