| Message ID | 20241012050611.1908-3-linux.amoon@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PCIe RK3399 clock and reset using new helper functions | expand |
On Sat, Oct 12, 2024 at 10:36:04AM +0530, Anand Moon wrote: > Refactor the reset control handling in the Rockchip PCIe driver, > introducing a more robust and efficient method for assert and > deassert reset controller using reset_control_bulk*() API. Using the > reset_control_bulk APIs, the reset handling for the core clocks reset > unit becomes much simpler. > Same comments as previous patch. > Spilt the reset controller in two groups as pre the RK3399 TRM. *per Also please state the TRM name and section for reference. > After power up, the software driver should de-assert the reset of PCIe PHY, > then wait the PLL locked by polling the status, if PLL > has locked, then can de-assert the reset simultaneously > driver need to De-assert the reset pins simultionaly. > > PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N. > > - replace devm_reset_control_get_exclusive() with > devm_reset_control_bulk_get_exclusive(). > - replace reset_control_assert with > reset_control_bulk_assert(). > - replace reset_control_deassert with > reset_control_bulk_deassert(). > > Signed-off-by: Anand Moon <linux.amoon@gmail.com> > --- > v7: replace devm_reset_control_bulk_get_optional_exclusive() > with devm_reset_control_bulk_get_exclusive() > update the functional changes. > V6: Add reason for the split of the RESET pins. > v5: Fix the De-assert reset core as per the TRM > De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N > simultaneously. > v4: use dev_err_probe in error path. > v3: Fix typo in commit message, dropped reported by. > v2: Fix compilation error reported by Intel test robot > fixed checkpatch warning. > --- > drivers/pci/controller/pcie-rockchip.c | 151 +++++-------------------- > drivers/pci/controller/pcie-rockchip.h | 26 +++-- > 2 files changed, 49 insertions(+), 128 deletions(-) > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c > index 2777ef0cb599..9a118e2b8cbd 100644 > --- a/drivers/pci/controller/pcie-rockchip.c > +++ b/drivers/pci/controller/pcie-rockchip.c > @@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) [...] > + err = reset_control_bulk_assert(ROCKCHIP_NUM_PM_RSTS, > + rockchip->pm_rsts); > + if (err) > + return dev_err_probe(dev, err, "reset bulk assert pm reset\n"); 'Couldn't assert PM resets' > > for (i = 0; i < MAX_LANE_NUM; i++) { > err = phy_init(rockchip->phys[i]); > @@ -173,47 +128,17 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > } > } > > - err = reset_control_assert(rockchip->core_rst); > - if (err) { > - dev_err(dev, "assert core_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_assert(rockchip->mgmt_rst); > - if (err) { > - dev_err(dev, "assert mgmt_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_assert(rockchip->mgmt_sticky_rst); > - if (err) { > - dev_err(dev, "assert mgmt_sticky_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_assert(rockchip->pipe_rst); > - if (err) { > - dev_err(dev, "assert pipe_rst err %d\n", err); > - goto err_exit_phy; > - } > + err = reset_control_bulk_assert(ROCKCHIP_NUM_CORE_RSTS, > + rockchip->core_rsts); > + if (err) > + return dev_err_probe(dev, err, "reset bulk assert core reset\n"); 'Couldn't assert Core resets' > > udelay(10); > > - err = reset_control_deassert(rockchip->pm_rst); > - if (err) { > - dev_err(dev, "deassert pm_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_deassert(rockchip->aclk_rst); > + err = reset_control_bulk_deassert(ROCKCHIP_NUM_PM_RSTS, > + rockchip->pm_rsts); > if (err) { > - dev_err(dev, "deassert aclk_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_deassert(rockchip->pclk_rst); > - if (err) { > - dev_err(dev, "deassert pclk_rst err %d\n", err); > + dev_err(dev, "reset bulk deassert pm err %d\n", err); 'Couldn't deassert PM resets' > goto err_exit_phy; > } > > @@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > * Please don't reorder the deassert sequence of the following > * four reset pins. I don't think my earlier comment on this addressed. Why are you changing the reset order? Why can't you have the resets in below (older) order? static const char * const rockchip_pci_core_rsts[] = { mgmt-sticky", "core", "mgmt", "pipe", }; Also, this comment should be removed now. > */ > - err = reset_control_deassert(rockchip->mgmt_sticky_rst); > - if (err) { > - dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); > - goto err_power_off_phy; > - } > - > - err = reset_control_deassert(rockchip->core_rst); > + err = reset_control_bulk_deassert(ROCKCHIP_NUM_CORE_RSTS, > + rockchip->core_rsts); > if (err) { > - dev_err(dev, "deassert core_rst err %d\n", err); > - goto err_power_off_phy; > - } > - > - err = reset_control_deassert(rockchip->mgmt_rst); > - if (err) { > - dev_err(dev, "deassert mgmt_rst err %d\n", err); > - goto err_power_off_phy; > - } > - > - err = reset_control_deassert(rockchip->pipe_rst); > - if (err) { > - dev_err(dev, "deassert pipe_rst err %d\n", err); > + dev_err(dev, "reset bulk deassert core err %d\n", err); 'Couldn't deassert Core resets' - Mani
Hi Manivannan, Thanks for your review comments. On Sat, 12 Oct 2024 at 11:48, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote: > > On Sat, Oct 12, 2024 at 10:36:04AM +0530, Anand Moon wrote: > > Refactor the reset control handling in the Rockchip PCIe driver, > > introducing a more robust and efficient method for assert and > > deassert reset controller using reset_control_bulk*() API. Using the > > reset_control_bulk APIs, the reset handling for the core clocks reset > > unit becomes much simpler. > > > > Same comments as previous patch. > I will explain more about this. > > Spilt the reset controller in two groups as pre the RK3399 TRM. > > *per > > Also please state the TRM name and section for reference. > Yes > > After power up, the software driver should de-assert the reset of PCIe PHY, > > then wait the PLL locked by polling the status, if PLL > > has locked, then can de-assert the reset simultaneously > > driver need to De-assert the reset pins simultionaly. > > > > PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N. > > > > - replace devm_reset_control_get_exclusive() with > > devm_reset_control_bulk_get_exclusive(). > > - replace reset_control_assert with > > reset_control_bulk_assert(). > > - replace reset_control_deassert with > > reset_control_bulk_deassert(). > > > > Signed-off-by: Anand Moon <linux.amoon@gmail.com> > > --- > > v7: replace devm_reset_control_bulk_get_optional_exclusive() > > with devm_reset_control_bulk_get_exclusive() > > update the functional changes. > > V6: Add reason for the split of the RESET pins. > > v5: Fix the De-assert reset core as per the TRM > > De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N > > simultaneously. > > v4: use dev_err_probe in error path. > > v3: Fix typo in commit message, dropped reported by. > > v2: Fix compilation error reported by Intel test robot > > fixed checkpatch warning. > > --- > > drivers/pci/controller/pcie-rockchip.c | 151 +++++-------------------- > > drivers/pci/controller/pcie-rockchip.h | 26 +++-- > > 2 files changed, 49 insertions(+), 128 deletions(-) > > > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c > > index 2777ef0cb599..9a118e2b8cbd 100644 > > --- a/drivers/pci/controller/pcie-rockchip.c > > +++ b/drivers/pci/controller/pcie-rockchip.c > > @@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) > > [...] > > > + err = reset_control_bulk_assert(ROCKCHIP_NUM_PM_RSTS, > > + rockchip->pm_rsts); > > + if (err) > > + return dev_err_probe(dev, err, "reset bulk assert pm reset\n"); > > 'Couldn't assert PM resets' > > > > > for (i = 0; i < MAX_LANE_NUM; i++) { > > err = phy_init(rockchip->phys[i]); > > @@ -173,47 +128,17 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > > } > > } > > > > - err = reset_control_assert(rockchip->core_rst); > > - if (err) { > > - dev_err(dev, "assert core_rst err %d\n", err); > > - goto err_exit_phy; > > - } > > - > > - err = reset_control_assert(rockchip->mgmt_rst); > > - if (err) { > > - dev_err(dev, "assert mgmt_rst err %d\n", err); > > - goto err_exit_phy; > > - } > > - > > - err = reset_control_assert(rockchip->mgmt_sticky_rst); > > - if (err) { > > - dev_err(dev, "assert mgmt_sticky_rst err %d\n", err); > > - goto err_exit_phy; > > - } > > - > > - err = reset_control_assert(rockchip->pipe_rst); > > - if (err) { > > - dev_err(dev, "assert pipe_rst err %d\n", err); > > - goto err_exit_phy; > > - } > > + err = reset_control_bulk_assert(ROCKCHIP_NUM_CORE_RSTS, > > + rockchip->core_rsts); > > + if (err) > > + return dev_err_probe(dev, err, "reset bulk assert core reset\n"); > > 'Couldn't assert Core resets' > > > > > udelay(10); > > > > - err = reset_control_deassert(rockchip->pm_rst); > > - if (err) { > > - dev_err(dev, "deassert pm_rst err %d\n", err); > > - goto err_exit_phy; > > - } > > - > > - err = reset_control_deassert(rockchip->aclk_rst); > > + err = reset_control_bulk_deassert(ROCKCHIP_NUM_PM_RSTS, > > + rockchip->pm_rsts); > > if (err) { > > - dev_err(dev, "deassert aclk_rst err %d\n", err); > > - goto err_exit_phy; > > - } > > - > > - err = reset_control_deassert(rockchip->pclk_rst); > > - if (err) { > > - dev_err(dev, "deassert pclk_rst err %d\n", err); > > + dev_err(dev, "reset bulk deassert pm err %d\n", err); > > 'Couldn't deassert PM resets' > > > goto err_exit_phy; > > } > > > > @@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > > * Please don't reorder the deassert sequence of the following > > * four reset pins. > > I don't think my earlier comment on this addressed. Why are you changing the > reset order? Why can't you have the resets in below (older) order? > > static const char * const rockchip_pci_core_rsts[] = { > mgmt-sticky", > "core", > "mgmt", > "pipe", > }; I will add a comment on this above. > > Also, this comment should be removed now. > > > */ > > - err = reset_control_deassert(rockchip->mgmt_sticky_rst); > > - if (err) { > > - dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); > > - goto err_power_off_phy; > > - } > > - > > - err = reset_control_deassert(rockchip->core_rst); > > + err = reset_control_bulk_deassert(ROCKCHIP_NUM_CORE_RSTS, > > + rockchip->core_rsts); > > if (err) { > > - dev_err(dev, "deassert core_rst err %d\n", err); > > - goto err_power_off_phy; > > - } > > - > > - err = reset_control_deassert(rockchip->mgmt_rst); > > - if (err) { > > - dev_err(dev, "deassert mgmt_rst err %d\n", err); > > - goto err_power_off_phy; > > - } > > - > > - err = reset_control_deassert(rockchip->pipe_rst); > > - if (err) { > > - dev_err(dev, "deassert pipe_rst err %d\n", err); > > + dev_err(dev, "reset bulk deassert core err %d\n", err); > > 'Couldn't deassert Core resets' > > - Mani > > -- > மணிவண்ணன் சதாசிவம் Ok,I will try to improve this in the next version. Thanks -Anand
On Sat, Oct 12, 2024 at 12:55:32PM +0530, Anand Moon wrote: > Hi Manivannan, > > Thanks for your review comments. > > On Sat, 12 Oct 2024 at 11:48, Manivannan Sadhasivam > <manivannan.sadhasivam@linaro.org> wrote: > > > > On Sat, Oct 12, 2024 at 10:36:04AM +0530, Anand Moon wrote: > > > Refactor the reset control handling in the Rockchip PCIe driver, > > > introducing a more robust and efficient method for assert and > > > deassert reset controller using reset_control_bulk*() API. Using the > > > reset_control_bulk APIs, the reset handling for the core clocks reset > > > unit becomes much simpler. > > > > > > > Same comments as previous patch. > > > I will explain more about this. > > > Spilt the reset controller in two groups as pre the RK3399 TRM. > > > > *per > > > > Also please state the TRM name and section for reference. > > > Yes > > > After power up, the software driver should de-assert the reset of PCIe PHY, > > > then wait the PLL locked by polling the status, if PLL > > > has locked, then can de-assert the reset simultaneously > > > driver need to De-assert the reset pins simultionaly. > > > > > > PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N. > > > > > > - replace devm_reset_control_get_exclusive() with > > > devm_reset_control_bulk_get_exclusive(). > > > - replace reset_control_assert with > > > reset_control_bulk_assert(). > > > - replace reset_control_deassert with > > > reset_control_bulk_deassert(). > > > > > > Signed-off-by: Anand Moon <linux.amoon@gmail.com> > > > --- > > > v7: replace devm_reset_control_bulk_get_optional_exclusive() > > > with devm_reset_control_bulk_get_exclusive() > > > update the functional changes. > > > V6: Add reason for the split of the RESET pins. > > > v5: Fix the De-assert reset core as per the TRM > > > De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N > > > simultaneously. > > > v4: use dev_err_probe in error path. > > > v3: Fix typo in commit message, dropped reported by. > > > v2: Fix compilation error reported by Intel test robot > > > fixed checkpatch warning. > > > --- > > > drivers/pci/controller/pcie-rockchip.c | 151 +++++-------------------- > > > drivers/pci/controller/pcie-rockchip.h | 26 +++-- > > > 2 files changed, 49 insertions(+), 128 deletions(-) > > > > > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c > > > index 2777ef0cb599..9a118e2b8cbd 100644 > > > --- a/drivers/pci/controller/pcie-rockchip.c > > > +++ b/drivers/pci/controller/pcie-rockchip.c [...] > > > @@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > > > * Please don't reorder the deassert sequence of the following > > > * four reset pins. > > > > I don't think my earlier comment on this addressed. Why are you changing the > > reset order? Why can't you have the resets in below (older) order? > > > > static const char * const rockchip_pci_core_rsts[] = { > > mgmt-sticky", > > "core", > > "mgmt", > > "pipe", > > }; > I will add a comment on this above. Sorry, I don't get your response. My suggestion was to keep the resets sorted as the original order (also indicated by my above snippet). - Mani
Hi Manivannan, On Sat, 12 Oct 2024 at 13:30, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote: > > On Sat, Oct 12, 2024 at 12:55:32PM +0530, Anand Moon wrote: > > Hi Manivannan, > > > > Thanks for your review comments. > > > > On Sat, 12 Oct 2024 at 11:48, Manivannan Sadhasivam > > <manivannan.sadhasivam@linaro.org> wrote: > > > > > > On Sat, Oct 12, 2024 at 10:36:04AM +0530, Anand Moon wrote: > > > > Refactor the reset control handling in the Rockchip PCIe driver, > > > > introducing a more robust and efficient method for assert and > > > > deassert reset controller using reset_control_bulk*() API. Using the > > > > reset_control_bulk APIs, the reset handling for the core clocks reset > > > > unit becomes much simpler. > > > > > > > > > > Same comments as previous patch. > > > > > I will explain more about this. > > > > Spilt the reset controller in two groups as pre the RK3399 TRM. > > > > > > *per > > > > > > Also please state the TRM name and section for reference. > > > > > Yes > > > > After power up, the software driver should de-assert the reset of PCIe PHY, > > > > then wait the PLL locked by polling the status, if PLL > > > > has locked, then can de-assert the reset simultaneously > > > > driver need to De-assert the reset pins simultionaly. > > > > > > > > PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N. > > > > > > > > - replace devm_reset_control_get_exclusive() with > > > > devm_reset_control_bulk_get_exclusive(). > > > > - replace reset_control_assert with > > > > reset_control_bulk_assert(). > > > > - replace reset_control_deassert with > > > > reset_control_bulk_deassert(). > > > > > > > > Signed-off-by: Anand Moon <linux.amoon@gmail.com> > > > > --- > > > > v7: replace devm_reset_control_bulk_get_optional_exclusive() > > > > with devm_reset_control_bulk_get_exclusive() > > > > update the functional changes. > > > > V6: Add reason for the split of the RESET pins. > > > > v5: Fix the De-assert reset core as per the TRM > > > > De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N > > > > simultaneously. > > > > v4: use dev_err_probe in error path. > > > > v3: Fix typo in commit message, dropped reported by. > > > > v2: Fix compilation error reported by Intel test robot > > > > fixed checkpatch warning. > > > > --- > > > > drivers/pci/controller/pcie-rockchip.c | 151 +++++-------------------- > > > > drivers/pci/controller/pcie-rockchip.h | 26 +++-- > > > > 2 files changed, 49 insertions(+), 128 deletions(-) > > > > > > > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c > > > > index 2777ef0cb599..9a118e2b8cbd 100644 > > > > --- a/drivers/pci/controller/pcie-rockchip.c > > > > +++ b/drivers/pci/controller/pcie-rockchip.c > > [...] > > > > > @@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > > > > * Please don't reorder the deassert sequence of the following > > > > * four reset pins. > > > > > > I don't think my earlier comment on this addressed. Why are you changing the > > > reset order? Why can't you have the resets in below (older) order? > > > > > > static const char * const rockchip_pci_core_rsts[] = { > > > mgmt-sticky", > > > "core", > > > "mgmt", > > > "pipe", > > > }; > > I will add a comment on this above. I get your point, I missed your point. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-rockchip.c?h=v6.12-rc2#n275 Actually I had these changes, but it got missed out in rebase. > > Sorry, I don't get your response. My suggestion was to keep the resets sorted as > the original order (also indicated by my above snippet). I will go through all the suggestions and modify them accordingly. As per the RK3399 TRM [2] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf 17.5.2.2 Reset Application 17.5.2.2.2 System Reset (describe all the core reset feature) (name as per the dts mapping) RESET_N: - core MGMT_RESET_N:- mgmt MGMT_STICKY_RESET_N:- mgmt-sticky PIPE_RESET_N: - pipe AXI_RESET_N - aclk APB_RESET_N: pclk PM_RESET_N: - pm PCIE_PHY_RESET_N: - phy reset (used in the phy driver). This is the reason for the split of the clk and core reset. Further down in 17.5.8 PCIe Operation 17.5.8.1 PCIe Initialization Sequence 17.5.8.1.1 PCIe as Root Complex 6. De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously Should I follow this order ? or the above order. static const char * const rockchip_pci_core_rsts[] = { "pipe", "mgmt-sticky", "mgmt", "core", }; > > - Mani > > -- > மணிவண்ணன் சதாசிவம் Thanks -Anand
On Sat, Oct 12, 2024 at 03:34:25PM +0530, Anand Moon wrote: > Hi Manivannan, > > On Sat, 12 Oct 2024 at 13:30, Manivannan Sadhasivam > <manivannan.sadhasivam@linaro.org> wrote: > > > > On Sat, Oct 12, 2024 at 12:55:32PM +0530, Anand Moon wrote: > > > Hi Manivannan, > > > > > > Thanks for your review comments. > > > > > > On Sat, 12 Oct 2024 at 11:48, Manivannan Sadhasivam > > > <manivannan.sadhasivam@linaro.org> wrote: > > > > > > > > On Sat, Oct 12, 2024 at 10:36:04AM +0530, Anand Moon wrote: > > > > > Refactor the reset control handling in the Rockchip PCIe driver, > > > > > introducing a more robust and efficient method for assert and > > > > > deassert reset controller using reset_control_bulk*() API. Using the > > > > > reset_control_bulk APIs, the reset handling for the core clocks reset > > > > > unit becomes much simpler. > > > > > > > > > > > > > Same comments as previous patch. > > > > > > > I will explain more about this. > > > > > Spilt the reset controller in two groups as pre the RK3399 TRM. > > > > > > > > *per > > > > > > > > Also please state the TRM name and section for reference. > > > > > > > Yes > > > > > After power up, the software driver should de-assert the reset of PCIe PHY, > > > > > then wait the PLL locked by polling the status, if PLL > > > > > has locked, then can de-assert the reset simultaneously > > > > > driver need to De-assert the reset pins simultionaly. > > > > > > > > > > PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N. > > > > > > > > > > - replace devm_reset_control_get_exclusive() with > > > > > devm_reset_control_bulk_get_exclusive(). > > > > > - replace reset_control_assert with > > > > > reset_control_bulk_assert(). > > > > > - replace reset_control_deassert with > > > > > reset_control_bulk_deassert(). > > > > > > > > > > Signed-off-by: Anand Moon <linux.amoon@gmail.com> > > > > > --- > > > > > v7: replace devm_reset_control_bulk_get_optional_exclusive() > > > > > with devm_reset_control_bulk_get_exclusive() > > > > > update the functional changes. > > > > > V6: Add reason for the split of the RESET pins. > > > > > v5: Fix the De-assert reset core as per the TRM > > > > > De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N > > > > > simultaneously. > > > > > v4: use dev_err_probe in error path. > > > > > v3: Fix typo in commit message, dropped reported by. > > > > > v2: Fix compilation error reported by Intel test robot > > > > > fixed checkpatch warning. > > > > > --- > > > > > drivers/pci/controller/pcie-rockchip.c | 151 +++++-------------------- > > > > > drivers/pci/controller/pcie-rockchip.h | 26 +++-- > > > > > 2 files changed, 49 insertions(+), 128 deletions(-) > > > > > > > > > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c > > > > > index 2777ef0cb599..9a118e2b8cbd 100644 > > > > > --- a/drivers/pci/controller/pcie-rockchip.c > > > > > +++ b/drivers/pci/controller/pcie-rockchip.c > > > > [...] > > > > > > > @@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > > > > > * Please don't reorder the deassert sequence of the following > > > > > * four reset pins. > > > > > > > > I don't think my earlier comment on this addressed. Why are you changing the > > > > reset order? Why can't you have the resets in below (older) order? > > > > > > > > static const char * const rockchip_pci_core_rsts[] = { > > > > mgmt-sticky", > > > > "core", > > > > "mgmt", > > > > "pipe", > > > > }; > > > I will add a comment on this above. > > I get your point, I missed your point. > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-rockchip.c?h=v6.12-rc2#n275 > > Actually I had these changes, but it got missed out in rebase. > > > > > Sorry, I don't get your response. My suggestion was to keep the resets sorted as > > the original order (also indicated by my above snippet). > > I will go through all the suggestions and modify them accordingly. > > As per the RK3399 TRM > [2] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf > > 17.5.2.2 Reset Application > 17.5.2.2.2 System Reset (describe all the core reset feature) > (name as per the dts mapping) > RESET_N: - core > MGMT_RESET_N:- mgmt > MGMT_STICKY_RESET_N:- mgmt-sticky > PIPE_RESET_N: - pipe > AXI_RESET_N - aclk > APB_RESET_N: pclk > PM_RESET_N: - pm > PCIE_PHY_RESET_N: - phy reset (used in the phy driver). > > This is the reason for the split of the clk and core reset. > > Further down in > 17.5.8 PCIe Operation > 17.5.8.1 PCIe Initialization Sequence > 17.5.8.1.1 PCIe as Root Complex > > 6. De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N > simultaneously > > Should I follow this order ? or the above order. > static const char * const rockchip_pci_core_rsts[] = { > "pipe", > "mgmt-sticky", > "mgmt", > "core", > }; Ok, thanks for clarifying. I was worried about the comment in the driver that warns against changing the order. But TRM rececommends a different order :/ But since no one ever reported any issue, let's go with the existing order. If you want to follow TRM, then I'd like to get an Ack from Rockchip Engineers who knows the hardware better. - Mani
Hi Manivannan, On Sat, 12 Oct 2024 at 17:35, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote: > > On Sat, Oct 12, 2024 at 03:34:25PM +0530, Anand Moon wrote: > > Hi Manivannan, > > > > On Sat, 12 Oct 2024 at 13:30, Manivannan Sadhasivam > > <manivannan.sadhasivam@linaro.org> wrote: > > > > > > On Sat, Oct 12, 2024 at 12:55:32PM +0530, Anand Moon wrote: > > > > Hi Manivannan, > > > > > > > > Thanks for your review comments. > > > > > > > > On Sat, 12 Oct 2024 at 11:48, Manivannan Sadhasivam > > > > <manivannan.sadhasivam@linaro.org> wrote: > > > > > > > > > > On Sat, Oct 12, 2024 at 10:36:04AM +0530, Anand Moon wrote: > > > > > > Refactor the reset control handling in the Rockchip PCIe driver, > > > > > > introducing a more robust and efficient method for assert and > > > > > > deassert reset controller using reset_control_bulk*() API. Using the > > > > > > reset_control_bulk APIs, the reset handling for the core clocks reset > > > > > > unit becomes much simpler. > > > > > > > > > > > > > > > > Same comments as previous patch. > > > > > > > > > I will explain more about this. > > > > > > Spilt the reset controller in two groups as pre the RK3399 TRM. > > > > > > > > > > *per > > > > > > > > > > Also please state the TRM name and section for reference. > > > > > > > > > Yes > > > > > > After power up, the software driver should de-assert the reset of PCIe PHY, > > > > > > then wait the PLL locked by polling the status, if PLL > > > > > > has locked, then can de-assert the reset simultaneously > > > > > > driver need to De-assert the reset pins simultionaly. > > > > > > > > > > > > PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N. > > > > > > > > > > > > - replace devm_reset_control_get_exclusive() with > > > > > > devm_reset_control_bulk_get_exclusive(). > > > > > > - replace reset_control_assert with > > > > > > reset_control_bulk_assert(). > > > > > > - replace reset_control_deassert with > > > > > > reset_control_bulk_deassert(). > > > > > > > > > > > > Signed-off-by: Anand Moon <linux.amoon@gmail.com> > > > > > > --- > > > > > > v7: replace devm_reset_control_bulk_get_optional_exclusive() > > > > > > with devm_reset_control_bulk_get_exclusive() > > > > > > update the functional changes. > > > > > > V6: Add reason for the split of the RESET pins. > > > > > > v5: Fix the De-assert reset core as per the TRM > > > > > > De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N > > > > > > simultaneously. > > > > > > v4: use dev_err_probe in error path. > > > > > > v3: Fix typo in commit message, dropped reported by. > > > > > > v2: Fix compilation error reported by Intel test robot > > > > > > fixed checkpatch warning. > > > > > > --- > > > > > > drivers/pci/controller/pcie-rockchip.c | 151 +++++-------------------- > > > > > > drivers/pci/controller/pcie-rockchip.h | 26 +++-- > > > > > > 2 files changed, 49 insertions(+), 128 deletions(-) > > > > > > > > > > > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c > > > > > > index 2777ef0cb599..9a118e2b8cbd 100644 > > > > > > --- a/drivers/pci/controller/pcie-rockchip.c > > > > > > +++ b/drivers/pci/controller/pcie-rockchip.c > > > > > > [...] > > > > > > > > > @@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > > > > > > * Please don't reorder the deassert sequence of the following > > > > > > * four reset pins. > > > > > > > > > > I don't think my earlier comment on this addressed. Why are you changing the > > > > > reset order? Why can't you have the resets in below (older) order? > > > > > > > > > > static const char * const rockchip_pci_core_rsts[] = { > > > > > mgmt-sticky", > > > > > "core", > > > > > "mgmt", > > > > > "pipe", > > > > > }; > > > > I will add a comment on this above. > > > > I get your point, I missed your point. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-rockchip.c?h=v6.12-rc2#n275 > > > > Actually I had these changes, but it got missed out in rebase. > > > > > > > > Sorry, I don't get your response. My suggestion was to keep the resets sorted as > > > the original order (also indicated by my above snippet). > > > > I will go through all the suggestions and modify them accordingly. > > > > As per the RK3399 TRM > > [2] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf > > > > 17.5.2.2 Reset Application > > 17.5.2.2.2 System Reset (describe all the core reset feature) > > (name as per the dts mapping) > > RESET_N: - core > > MGMT_RESET_N:- mgmt > > MGMT_STICKY_RESET_N:- mgmt-sticky > > PIPE_RESET_N: - pipe > > AXI_RESET_N - aclk > > APB_RESET_N: pclk > > PM_RESET_N: - pm > > PCIE_PHY_RESET_N: - phy reset (used in the phy driver). > > > > This is the reason for the split of the clk and core reset. > > > > Further down in > > 17.5.8 PCIe Operation > > 17.5.8.1 PCIe Initialization Sequence > > 17.5.8.1.1 PCIe as Root Complex > > > > 6. De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N > > simultaneously > > > > Should I follow this order ? or the above order. > > static const char * const rockchip_pci_core_rsts[] = { > > "pipe", > > "mgmt-sticky", > > "mgmt", > > "core", > > }; > > Ok, thanks for clarifying. I was worried about the comment in the driver that > warns against changing the order. But TRM rececommends a different order :/ > > But since no one ever reported any issue, let's go with the existing order. If > you want to follow TRM, then I'd like to get an Ack from Rockchip Engineers who > knows the hardware better. > I will follow the existing code version, I was confused with the name and description earlier. > - Mani > > -- > மணிவண்ணன் சதாசிவம் Thanks -Anand
diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index 2777ef0cb599..9a118e2b8cbd 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) struct platform_device *pdev = to_platform_device(dev); struct device_node *node = dev->of_node; struct resource *regs; - int err; + int err, i; if (rockchip->is_rc) { regs = platform_get_resource_byname(pdev, @@ -69,55 +69,23 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) if (rockchip->link_gen < 0 || rockchip->link_gen > 2) rockchip->link_gen = 2; - rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core"); - if (IS_ERR(rockchip->core_rst)) { - if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER) - dev_err(dev, "missing core reset property in node\n"); - return PTR_ERR(rockchip->core_rst); - } - - rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt"); - if (IS_ERR(rockchip->mgmt_rst)) { - if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER) - dev_err(dev, "missing mgmt reset property in node\n"); - return PTR_ERR(rockchip->mgmt_rst); - } - - rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev, - "mgmt-sticky"); - if (IS_ERR(rockchip->mgmt_sticky_rst)) { - if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER) - dev_err(dev, "missing mgmt-sticky reset property in node\n"); - return PTR_ERR(rockchip->mgmt_sticky_rst); - } - - rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe"); - if (IS_ERR(rockchip->pipe_rst)) { - if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER) - dev_err(dev, "missing pipe reset property in node\n"); - return PTR_ERR(rockchip->pipe_rst); - } + for (i = 0; i < ROCKCHIP_NUM_PM_RSTS; i++) + rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i]; - rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm"); - if (IS_ERR(rockchip->pm_rst)) { - if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER) - dev_err(dev, "missing pm reset property in node\n"); - return PTR_ERR(rockchip->pm_rst); - } + err = devm_reset_control_bulk_get_exclusive(dev, + ROCKCHIP_NUM_PM_RSTS, + rockchip->pm_rsts); + if (err) + return dev_err_probe(dev, err, "cannot get the reset control\n"); - rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk"); - if (IS_ERR(rockchip->pclk_rst)) { - if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER) - dev_err(dev, "missing pclk reset property in node\n"); - return PTR_ERR(rockchip->pclk_rst); - } + for (i = 0; i < ROCKCHIP_NUM_CORE_RSTS; i++) + rockchip->core_rsts[i].id = rockchip_pci_core_rsts[i]; - rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk"); - if (IS_ERR(rockchip->aclk_rst)) { - if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER) - dev_err(dev, "missing aclk reset property in node\n"); - return PTR_ERR(rockchip->aclk_rst); - } + err = devm_reset_control_bulk_get_exclusive(dev, + ROCKCHIP_NUM_CORE_RSTS, + rockchip->core_rsts); + if (err) + return dev_err_probe(dev, err, "cannot get the reset control\n"); if (rockchip->is_rc) { rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep", @@ -147,23 +115,10 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) int err, i; u32 regs; - err = reset_control_assert(rockchip->aclk_rst); - if (err) { - dev_err(dev, "assert aclk_rst err %d\n", err); - return err; - } - - err = reset_control_assert(rockchip->pclk_rst); - if (err) { - dev_err(dev, "assert pclk_rst err %d\n", err); - return err; - } - - err = reset_control_assert(rockchip->pm_rst); - if (err) { - dev_err(dev, "assert pm_rst err %d\n", err); - return err; - } + err = reset_control_bulk_assert(ROCKCHIP_NUM_PM_RSTS, + rockchip->pm_rsts); + if (err) + return dev_err_probe(dev, err, "reset bulk assert pm reset\n"); for (i = 0; i < MAX_LANE_NUM; i++) { err = phy_init(rockchip->phys[i]); @@ -173,47 +128,17 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) } } - err = reset_control_assert(rockchip->core_rst); - if (err) { - dev_err(dev, "assert core_rst err %d\n", err); - goto err_exit_phy; - } - - err = reset_control_assert(rockchip->mgmt_rst); - if (err) { - dev_err(dev, "assert mgmt_rst err %d\n", err); - goto err_exit_phy; - } - - err = reset_control_assert(rockchip->mgmt_sticky_rst); - if (err) { - dev_err(dev, "assert mgmt_sticky_rst err %d\n", err); - goto err_exit_phy; - } - - err = reset_control_assert(rockchip->pipe_rst); - if (err) { - dev_err(dev, "assert pipe_rst err %d\n", err); - goto err_exit_phy; - } + err = reset_control_bulk_assert(ROCKCHIP_NUM_CORE_RSTS, + rockchip->core_rsts); + if (err) + return dev_err_probe(dev, err, "reset bulk assert core reset\n"); udelay(10); - err = reset_control_deassert(rockchip->pm_rst); - if (err) { - dev_err(dev, "deassert pm_rst err %d\n", err); - goto err_exit_phy; - } - - err = reset_control_deassert(rockchip->aclk_rst); + err = reset_control_bulk_deassert(ROCKCHIP_NUM_PM_RSTS, + rockchip->pm_rsts); if (err) { - dev_err(dev, "deassert aclk_rst err %d\n", err); - goto err_exit_phy; - } - - err = reset_control_deassert(rockchip->pclk_rst); - if (err) { - dev_err(dev, "deassert pclk_rst err %d\n", err); + dev_err(dev, "reset bulk deassert pm err %d\n", err); goto err_exit_phy; } @@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) * Please don't reorder the deassert sequence of the following * four reset pins. */ - err = reset_control_deassert(rockchip->mgmt_sticky_rst); - if (err) { - dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); - goto err_power_off_phy; - } - - err = reset_control_deassert(rockchip->core_rst); + err = reset_control_bulk_deassert(ROCKCHIP_NUM_CORE_RSTS, + rockchip->core_rsts); if (err) { - dev_err(dev, "deassert core_rst err %d\n", err); - goto err_power_off_phy; - } - - err = reset_control_deassert(rockchip->mgmt_rst); - if (err) { - dev_err(dev, "deassert mgmt_rst err %d\n", err); - goto err_power_off_phy; - } - - err = reset_control_deassert(rockchip->pipe_rst); - if (err) { - dev_err(dev, "deassert pipe_rst err %d\n", err); + dev_err(dev, "reset bulk deassert core err %d\n", err); goto err_power_off_phy; } return 0; + err_power_off_phy: while (i--) phy_power_off(rockchip->phys[i]); diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index bebab80c9553..2761699f670b 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -15,6 +15,7 @@ #include <linux/kernel.h> #include <linux/pci.h> #include <linux/pci-ecam.h> +#include <linux/reset.h> /* * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16 @@ -288,18 +289,29 @@ (((c) << ((b) * 8 + 5)) & \ ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) +#define ROCKCHIP_NUM_PM_RSTS ARRAY_SIZE(rockchip_pci_pm_rsts) +#define ROCKCHIP_NUM_CORE_RSTS ARRAY_SIZE(rockchip_pci_core_rsts) + +static const char * const rockchip_pci_pm_rsts[] = { + "pm", + "pclk", + "aclk", +}; + +static const char * const rockchip_pci_core_rsts[] = { + "mgmt-sticky", + "mgmt", + "core", + "pipe", +}; + struct rockchip_pcie { void __iomem *reg_base; /* DT axi-base */ void __iomem *apb_base; /* DT apb-base */ bool legacy_phy; struct phy *phys[MAX_LANE_NUM]; - struct reset_control *core_rst; - struct reset_control *mgmt_rst; - struct reset_control *mgmt_sticky_rst; - struct reset_control *pipe_rst; - struct reset_control *pm_rst; - struct reset_control *aclk_rst; - struct reset_control *pclk_rst; + struct reset_control_bulk_data pm_rsts[ROCKCHIP_NUM_PM_RSTS]; + struct reset_control_bulk_data core_rsts[ROCKCHIP_NUM_CORE_RSTS]; struct clk_bulk_data *clks; int num_clks; struct regulator *vpcie12v; /* 12V power supply */
Refactor the reset control handling in the Rockchip PCIe driver, introducing a more robust and efficient method for assert and deassert reset controller using reset_control_bulk*() API. Using the reset_control_bulk APIs, the reset handling for the core clocks reset unit becomes much simpler. Spilt the reset controller in two groups as pre the RK3399 TRM. After power up, the software driver should de-assert the reset of PCIe PHY, then wait the PLL locked by polling the status, if PLL has locked, then can de-assert the reset simultaneously driver need to De-assert the reset pins simultionaly. PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N. - replace devm_reset_control_get_exclusive() with devm_reset_control_bulk_get_exclusive(). - replace reset_control_assert with reset_control_bulk_assert(). - replace reset_control_deassert with reset_control_bulk_deassert(). Signed-off-by: Anand Moon <linux.amoon@gmail.com> --- v7: replace devm_reset_control_bulk_get_optional_exclusive() with devm_reset_control_bulk_get_exclusive() update the functional changes. V6: Add reason for the split of the RESET pins. v5: Fix the De-assert reset core as per the TRM De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously. v4: use dev_err_probe in error path. v3: Fix typo in commit message, dropped reported by. v2: Fix compilation error reported by Intel test robot fixed checkpatch warning. --- drivers/pci/controller/pcie-rockchip.c | 151 +++++-------------------- drivers/pci/controller/pcie-rockchip.h | 26 +++-- 2 files changed, 49 insertions(+), 128 deletions(-)