| Message ID | 20241015-smmuv3-v1-0-e4b9ed1b5501@nxp.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | iommu/arm-smmu-v3: bypass streamid zero on i.MX95 | expand |
Hi Peng, On Tue, Oct 15, 2024 at 11:14:41AM +0800, Peng Fan (OSS) wrote: > i.MX95 eDMA3 connects to DSU ACP, supporting dma coherent memory to > memory operations. However TBU is in the path between eDMA3 and ACP, > need to bypass the default SID 0 to make eDMA3 work properly. > > I was also thinking to introduce "bypass-sids = <0xA 0xB 0xC ...>" to > make this reusable for others, but not sure. I could switch to > "bypass-sids" if you prefer. Any reason why you can't use the sysfs to change the iommu domain type? i.e. by using the /sys/kernel/iommu_groups/<iommu_group_number>/type AFAIK, the arm-smmu-v3 driver allocates one iommu_group per device. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > Peng Fan (2): > dt-bindings: iommu: arm,smmu-v3: introduce nxp,imx95-bypass-sid-zero > iommu/arm-smmu-v3: Bypass SID0 for NXP i.MX95 > > .../devicetree/bindings/iommu/arm,smmu-v3.yaml | 4 ++++ > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 19 ++++++++++++++++--- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + > 3 files changed, 21 insertions(+), 3 deletions(-) > --- > base-commit: d61a00525464bfc5fe92c6ad713350988e492b88 > change-id: 20241014-smmuv3-120b24bc4659 > > Best regards, > -- > Peng Fan <peng.fan@nxp.com> > > Thanks, Pranjal
On 2024-10-15 4:14 am, Peng Fan (OSS) wrote: > i.MX95 eDMA3 connects to DSU ACP, supporting dma coherent memory to > memory operations. However TBU is in the path between eDMA3 and ACP, > need to bypass the default SID 0 to make eDMA3 work properly. I'm confused, why not just describe that the device owns this StreamID in the DT the normal way, i.e, "iommus = <&smmu 0>;"? Thanks, Robin. > I was also thinking to introduce "bypass-sids = <0xA 0xB 0xC ...>" to > make this reusable for others, but not sure. I could switch to > "bypass-sids" if you prefer. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > Peng Fan (2): > dt-bindings: iommu: arm,smmu-v3: introduce nxp,imx95-bypass-sid-zero > iommu/arm-smmu-v3: Bypass SID0 for NXP i.MX95 > > .../devicetree/bindings/iommu/arm,smmu-v3.yaml | 4 ++++ > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 19 ++++++++++++++++--- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + > 3 files changed, 21 insertions(+), 3 deletions(-) > --- > base-commit: d61a00525464bfc5fe92c6ad713350988e492b88 > change-id: 20241014-smmuv3-120b24bc4659 > > Best regards,
Hi Robin, > Subject: Re: [PATCH RFC 0/2] iommu/arm-smmu-v3: bypass streamid > zero on i.MX95 > > On 2024-10-15 4:14 am, Peng Fan (OSS) wrote: > > i.MX95 eDMA3 connects to DSU ACP, supporting dma coherent > memory to > > memory operations. However TBU is in the path between eDMA3 > and ACP, > > need to bypass the default SID 0 to make eDMA3 work properly. > > I'm confused, why not just describe that the device owns this StreamID > in the DT the normal way, i.e, "iommus = <&smmu 0>;"? Current SMMU-v3 driver not support streamID sharing, but we have limited streamIDs(i.MX95 max supports 64 SIDs). However the eDMA supports 64 channels, each channel may have a SID, but not supported by current smmuv3 driver. We see smmu would degrade the performance in somecases, so we wanna to give user an option to bypass SMMU for eDMA. Thanks, Peng. > > Thanks, > Robin. > > > I was also thinking to introduce "bypass-sids = <0xA 0xB 0xC ...>" to > > make this reusable for others, but not sure. I could switch to > > "bypass-sids" if you prefer. > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > --- > > Peng Fan (2): > > dt-bindings: iommu: arm,smmu-v3: introduce nxp,imx95-bypass- > sid-zero > > iommu/arm-smmu-v3: Bypass SID0 for NXP i.MX95 > > > > .../devicetree/bindings/iommu/arm,smmu-v3.yaml | 4 ++++ > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 19 > ++++++++++++++++--- > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + > > 3 files changed, 21 insertions(+), 3 deletions(-) > > --- > > base-commit: d61a00525464bfc5fe92c6ad713350988e492b88 > > change-id: 20241014-smmuv3-120b24bc4659 > > > > Best regards,
On Wed, Oct 16, 2024 at 12:56:54AM +0000, Peng Fan wrote: > > Subject: Re: [PATCH RFC 0/2] iommu/arm-smmu-v3: bypass streamid > > zero on i.MX95 > > > > On 2024-10-15 4:14 am, Peng Fan (OSS) wrote: > > > i.MX95 eDMA3 connects to DSU ACP, supporting dma coherent > > memory to > > > memory operations. However TBU is in the path between eDMA3 > > and ACP, > > > need to bypass the default SID 0 to make eDMA3 work properly. > > > > I'm confused, why not just describe that the device owns this StreamID > > in the DT the normal way, i.e, "iommus = <&smmu 0>;"? > > Current SMMU-v3 driver not support streamID sharing, but we have > limited streamIDs(i.MX95 max supports 64 SIDs). However the eDMA > supports 64 channels, each channel may have a SID, but not supported > by current smmuv3 driver. > > We see smmu would degrade the performance in somecases, so > we wanna to give user an option to bypass SMMU for eDMA. If it's a system-wise global need, adding "iommu.passthrough=y" to the bootargs string should work for all trusted devices. And particular group can be changed to the IDENTITY domain too upon cmdline setting, e.g. echo identity | sudo tee /sys/class/pci_bus/0009\:01/device/iommu_group/type Thanks Nicolin
> Subject: Re: [PATCH RFC 0/2] iommu/arm-smmu-v3: bypass streamid > zero on i.MX95 > > On Wed, Oct 16, 2024 at 12:56:54AM +0000, Peng Fan wrote: > > > Subject: Re: [PATCH RFC 0/2] iommu/arm-smmu-v3: bypass > streamid zero > > > on i.MX95 > > > > > > On 2024-10-15 4:14 am, Peng Fan (OSS) wrote: > > > > i.MX95 eDMA3 connects to DSU ACP, supporting dma coherent > > > memory to > > > > memory operations. However TBU is in the path between eDMA3 > > > and ACP, > > > > need to bypass the default SID 0 to make eDMA3 work properly. > > > > > > I'm confused, why not just describe that the device owns this > > > StreamID in the DT the normal way, i.e, "iommus = <&smmu 0>;"? > > > > Current SMMU-v3 driver not support streamID sharing, but we have > > limited streamIDs(i.MX95 max supports 64 SIDs). However the eDMA > > supports 64 channels, each channel may have a SID, but not > supported > > by current smmuv3 driver. > > > > We see smmu would degrade the performance in somecases, so we > wanna to > > give user an option to bypass SMMU for eDMA. > > If it's a system-wise global need, adding "iommu.passthrough=y" > to the bootargs string should work for all trusted devices. And No. not system wide. > particular group can be changed to the IDENTITY domain too upon > cmdline setting, e.g. > echo identity | sudo tee > /sys/class/pci_bus/0009\:01/device/iommu_group/type This means I still need to put iommus = <&smmu 0> under the device tree node. Thanks, Peng. > > Thanks > Nicolin
On Wed, Oct 16, 2024 at 08:53:20AM +0000, Peng Fan wrote: > > Subject: Re: [PATCH RFC 0/2] iommu/arm-smmu-v3: bypass streamid > > zero on i.MX95 > > > > On Wed, Oct 16, 2024 at 12:56:54AM +0000, Peng Fan wrote: > > > > Subject: Re: [PATCH RFC 0/2] iommu/arm-smmu-v3: bypass > > streamid zero > > > > on i.MX95 > > > > > > > > On 2024-10-15 4:14 am, Peng Fan (OSS) wrote: > > > > > i.MX95 eDMA3 connects to DSU ACP, supporting dma coherent > > > > memory to > > > > > memory operations. However TBU is in the path between eDMA3 > > > > and ACP, > > > > > need to bypass the default SID 0 to make eDMA3 work properly. > > > > > > > > I'm confused, why not just describe that the device owns this > > > > StreamID in the DT the normal way, i.e, "iommus = <&smmu 0>;"? > > > > > > Current SMMU-v3 driver not support streamID sharing, but we have > > > limited streamIDs(i.MX95 max supports 64 SIDs). However the eDMA > > > supports 64 channels, each channel may have a SID, but not > > supported > > > by current smmuv3 driver. > > > > > > We see smmu would degrade the performance in somecases, so we > > wanna to > > > give user an option to bypass SMMU for eDMA. > > > > If it's a system-wise global need, adding "iommu.passthrough=y" > > to the bootargs string should work for all trusted devices. And > > No. not system wide. > > > particular group can be changed to the IDENTITY domain too upon > > cmdline setting, e.g. > > echo identity | sudo tee > > /sys/class/pci_bus/0009\:01/device/iommu_group/type > > This means I still need to put iommus = <&smmu 0> under > the device tree node. > Yes, otherwise the bypassing an unassigned SID isn't something that the community wouldn't prefer as it smashes a hole in security for everyone. Does your hardware have a way all the devices can configure/program SIDs or does the hardware have multiple devices that generate SID 0? If it's programmable, I'd suggest reserving streamID 0 for bypass and let the system work with the other 63. Apart from that, if you can guarantee that the `eDMA3` would always access a fixed region of memory, then maybe use RMRs to install bypass. > Thanks, > Peng. > > > > > Thanks > > Nicolin > Thanks, Pranjal
i.MX95 eDMA3 connects to DSU ACP, supporting dma coherent memory to memory operations. However TBU is in the path between eDMA3 and ACP, need to bypass the default SID 0 to make eDMA3 work properly. I was also thinking to introduce "bypass-sids = <0xA 0xB 0xC ...>" to make this reusable for others, but not sure. I could switch to "bypass-sids" if you prefer. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- Peng Fan (2): dt-bindings: iommu: arm,smmu-v3: introduce nxp,imx95-bypass-sid-zero iommu/arm-smmu-v3: Bypass SID0 for NXP i.MX95 .../devicetree/bindings/iommu/arm,smmu-v3.yaml | 4 ++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 19 ++++++++++++++++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 3 files changed, 21 insertions(+), 3 deletions(-) --- base-commit: d61a00525464bfc5fe92c6ad713350988e492b88 change-id: 20241014-smmuv3-120b24bc4659 Best regards,