| Message ID | 20241014081000.2844245-7-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for 3 VDSC engines 12 slices | expand |
Hi Ankit, kernel test robot noticed the following build warnings: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on next-20241015] [cannot apply to drm-intel/for-linux-next-fixes drm-tip/drm-tip linus/master v6.12-rc3] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Ankit-Nautiyal/drm-i915-display-Prepare-for-dsc-3-stream-splitter/20241014-161007 base: git://anongit.freedesktop.org/drm-intel for-linux-next patch link: https://lore.kernel.org/r/20241014081000.2844245-7-ankit.k.nautiyal%40intel.com patch subject: [PATCH 6/9] drm/i915/display: Add DSC pixel replication config: i386-defconfig (https://download.01.org/0day-ci/archive/20241016/202410160018.hjWyI23D-lkp@intel.com/config) compiler: clang version 18.1.8 (https://github.com/llvm/llvm-project 3b5b5c1ec4a3095ab096dd780e84d7ab81f3d7ff) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241016/202410160018.hjWyI23D-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202410160018.hjWyI23D-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/gpu/drm/i915/display/intel_vdsc.c:1022:6: warning: variable 'dss_ctl3' is uninitialized when used here [-Wuninitialized] 1022 | if (dss_ctl3 & DSC_PIXEL_REPLICATION_MASK) | ^~~~~~~~ drivers/gpu/drm/i915/display/intel_vdsc.c:991:34: note: initialize the variable 'dss_ctl3' to silence this warning 991 | u32 dss_ctl1, dss_ctl2, dss_ctl3; | ^ | = 0 1 warning generated. vim +/dss_ctl3 +1022 drivers/gpu/drm/i915/display/intel_vdsc.c 983 984 void intel_dsc_get_config(struct intel_crtc_state *crtc_state) 985 { 986 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 987 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 988 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 989 enum intel_display_power_domain power_domain; 990 intel_wakeref_t wakeref; 991 u32 dss_ctl1, dss_ctl2, dss_ctl3; 992 993 if (!intel_dsc_source_support(crtc_state)) 994 return; 995 996 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder); 997 998 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 999 if (!wakeref) 1000 return; 1001 1002 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder)); 1003 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder)); 1004 1005 if (IS_BATTLEMAGE(dev_priv)) 1006 dss_ctl3 = intel_de_read(dev_priv, BMG_PIPE_DSS_CTL3(crtc_state->cpu_transcoder)); 1007 1008 crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE; 1009 if (!crtc_state->dsc.compression_enable) 1010 goto out; 1011 1012 if (dss_ctl1 & JOINER_ENABLE) { 1013 if (dss_ctl2 & (VDSC2_ENABLE | SMALL_JOINER_CONFIG_3_ENGINES)) 1014 crtc_state->dsc.dsc_split = INTEL_DSC_SPLIT_3_STREAMS; 1015 1016 else if (dss_ctl2 & VDSC1_ENABLE) 1017 crtc_state->dsc.dsc_split = INTEL_DSC_SPLIT_2_STREAMS; 1018 } else { 1019 crtc_state->dsc.dsc_split = INTEL_DSC_SPLIT_DISABLED; 1020 } 1021 > 1022 if (dss_ctl3 & DSC_PIXEL_REPLICATION_MASK) 1023 crtc_state->dsc.pixel_replication_count = 1024 dss_ctl3 & DSC_PIXEL_REPLICATION_MASK; 1025 1026 intel_dsc_get_pps_config(crtc_state); 1027 out: 1028 intel_display_power_put(dev_priv, power_domain, wakeref); 1029 } 1030
Hi Ankit, kernel test robot noticed the following build errors: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on next-20241016] [cannot apply to drm-intel/for-linux-next-fixes drm-tip/drm-tip linus/master v6.12-rc3] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Ankit-Nautiyal/drm-i915-display-Prepare-for-dsc-3-stream-splitter/20241014-161007 base: git://anongit.freedesktop.org/drm-intel for-linux-next patch link: https://lore.kernel.org/r/20241014081000.2844245-7-ankit.k.nautiyal%40intel.com patch subject: [PATCH 6/9] drm/i915/display: Add DSC pixel replication config: x86_64-randconfig-012-20241015 (https://download.01.org/0day-ci/archive/20241016/202410161836.lQv7K89f-lkp@intel.com/config) compiler: clang version 18.1.8 (https://github.com/llvm/llvm-project 3b5b5c1ec4a3095ab096dd780e84d7ab81f3d7ff) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241016/202410161836.lQv7K89f-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202410161836.lQv7K89f-lkp@intel.com/ All errors (new ones prefixed by >>): >> drivers/gpu/drm/i915/display/intel_vdsc.c:1022:6: error: variable 'dss_ctl3' is uninitialized when used here [-Werror,-Wuninitialized] 1022 | if (dss_ctl3 & DSC_PIXEL_REPLICATION_MASK) | ^~~~~~~~ drivers/gpu/drm/i915/display/intel_vdsc.c:991:34: note: initialize the variable 'dss_ctl3' to silence this warning 991 | u32 dss_ctl1, dss_ctl2, dss_ctl3; | ^ | = 0 1 error generated. vim +/dss_ctl3 +1022 drivers/gpu/drm/i915/display/intel_vdsc.c 983 984 void intel_dsc_get_config(struct intel_crtc_state *crtc_state) 985 { 986 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 987 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 988 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 989 enum intel_display_power_domain power_domain; 990 intel_wakeref_t wakeref; 991 u32 dss_ctl1, dss_ctl2, dss_ctl3; 992 993 if (!intel_dsc_source_support(crtc_state)) 994 return; 995 996 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder); 997 998 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 999 if (!wakeref) 1000 return; 1001 1002 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder)); 1003 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder)); 1004 1005 if (IS_BATTLEMAGE(dev_priv)) 1006 dss_ctl3 = intel_de_read(dev_priv, BMG_PIPE_DSS_CTL3(crtc_state->cpu_transcoder)); 1007 1008 crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE; 1009 if (!crtc_state->dsc.compression_enable) 1010 goto out; 1011 1012 if (dss_ctl1 & JOINER_ENABLE) { 1013 if (dss_ctl2 & (VDSC2_ENABLE | SMALL_JOINER_CONFIG_3_ENGINES)) 1014 crtc_state->dsc.dsc_split = INTEL_DSC_SPLIT_3_STREAMS; 1015 1016 else if (dss_ctl2 & VDSC1_ENABLE) 1017 crtc_state->dsc.dsc_split = INTEL_DSC_SPLIT_2_STREAMS; 1018 } else { 1019 crtc_state->dsc.dsc_split = INTEL_DSC_SPLIT_DISABLED; 1020 } 1021 > 1022 if (dss_ctl3 & DSC_PIXEL_REPLICATION_MASK) 1023 crtc_state->dsc.pixel_replication_count = 1024 dss_ctl3 & DSC_PIXEL_REPLICATION_MASK; 1025 1026 intel_dsc_get_pps_config(crtc_state); 1027 out: 1028 intel_display_power_put(dev_priv, power_domain, wakeref); 1029 } 1030
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 86c7ac600122..5846f16f0ee9 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5725,6 +5725,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(dsc.compression_enable); PIPE_CONF_CHECK_I(dsc.dsc_split); PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); + PIPE_CONF_CHECK_I(dsc.pixel_replication_count); PIPE_CONF_CHECK_BOOL(splitter.enable); PIPE_CONF_CHECK_I(splitter.link_count); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index e6d37d28c5c1..41a4e062e047 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1245,6 +1245,7 @@ struct intel_crtc_state { /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */ u16 compressed_bpp_x16; u8 slice_count; + int pixel_replication_count; struct drm_dsc_config config; } dsc; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 982dc326b4a1..f58dac630bb8 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -774,6 +774,7 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dss_ctl1_val = 0; u32 dss_ctl2_val = 0; + u32 dss_ctl3_val = 0; int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); if (!crtc_state->dsc.compression_enable) @@ -804,8 +805,16 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) if (intel_crtc_is_bigjoiner_primary(crtc_state)) dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE; } + + if (crtc_state->dsc.pixel_replication_count) + dss_ctl3_val = DSC_PIXEL_REPLICATION(crtc_state->dsc.pixel_replication_count); + intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val); + + if (IS_BATTLEMAGE(dev_priv) && dss_ctl3_val) + intel_de_write(dev_priv, + BMG_PIPE_DSS_CTL3(crtc_state->cpu_transcoder), dss_ctl3_val); } void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) @@ -818,6 +827,10 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) old_crtc_state->joiner_pipes) { intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0); intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0); + + if (IS_BATTLEMAGE(dev_priv)) + intel_de_write(dev_priv, + BMG_PIPE_DSS_CTL3(old_crtc_state->cpu_transcoder), 0); } } @@ -975,7 +988,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; - u32 dss_ctl1, dss_ctl2; + u32 dss_ctl1, dss_ctl2, dss_ctl3; if (!intel_dsc_source_support(crtc_state)) return; @@ -989,6 +1002,9 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder)); dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder)); + if (IS_BATTLEMAGE(dev_priv)) + dss_ctl3 = intel_de_read(dev_priv, BMG_PIPE_DSS_CTL3(crtc_state->cpu_transcoder)); + crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE; if (!crtc_state->dsc.compression_enable) goto out; @@ -1003,6 +1019,10 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) crtc_state->dsc.dsc_split = INTEL_DSC_SPLIT_DISABLED; } + if (dss_ctl3 & DSC_PIXEL_REPLICATION_MASK) + crtc_state->dsc.pixel_replication_count = + dss_ctl3 & DSC_PIXEL_REPLICATION_MASK; + intel_dsc_get_pps_config(crtc_state); out: intel_display_power_put(dev_priv, power_domain, wakeref); diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index efaeb5e0aea3..a588ce61cba7 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -52,6 +52,14 @@ _ICL_PIPE_DSS_CTL2_PB, \ _ICL_PIPE_DSS_CTL2_PC) +#define _BMG_PIPE_DSS_CTL3_PB 0x782F0 +#define _BMG_PIPE_DSS_CTL3_PC 0x784F0 +#define BMG_PIPE_DSS_CTL3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _BMG_PIPE_DSS_CTL3_PB, \ + _BMG_PIPE_DSS_CTL3_PC) +#define DSC_PIXEL_REPLICATION_MASK REG_GENMASK(15, 0) +#define DSC_PIXEL_REPLICATION(count) ((count) << 0) + /* Icelake Display Stream Compression Registers */ #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
With 3 VDSC engines and Ultrajoiner, we may encounter a situation where hdisplay is not a multiple of slice count. In this case we need to add extra pixels to the last slice to distribute pixels evenly across slices. Add member to store DSC pixel replication when hdisplay is not divisible by slice_width. Fill DSS_CTL3 register with the pixel replication count. TODO: 1. Scaler: If the DSC is enabled and pixel replication is occurring, then the scaler window size and position must fit within the pipe active size plus the pixel replication. 2. PIPE_SRC: Horizontal Src size must always be programmed to the same value as the Horizontal Active except when panel fitting is enabled or DSC pixel replication is enabled. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 1 + .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_vdsc.c | 22 ++++++++++++++++++- .../gpu/drm/i915/display/intel_vdsc_regs.h | 8 +++++++ 4 files changed, 31 insertions(+), 1 deletion(-)