| Message ID | 20241017-sar2130p-clocks-v1-9-f75e740f0a8d@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: qcom: add support for clock controllers on the SAR2130P platform | expand |
On 10/17/2024 10:26 PM, Dmitry Baryshkov wrote: > Some platforms use separate collapse vote registers for the active and > sleep states. Extend gdsc_update_collapse_bit() to support separate > collapse_sleep_ctrl register. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/clk/qcom/gdsc.c | 8 ++++++++ > drivers/clk/qcom/gdsc.h | 2 ++ > 2 files changed, 10 insertions(+) > > diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c > index fa5fe4c2a2ee7786c2e8858f3e41301f639e5d59..95f8e90a8d25673c8a97a03f92cbdad25c3259db 100644 > --- a/drivers/clk/qcom/gdsc.c > +++ b/drivers/clk/qcom/gdsc.c > @@ -133,6 +133,14 @@ static int gdsc_update_collapse_bit(struct gdsc *sc, bool val) > if (ret) > return ret; > > + if (sc->collapse_sleep_ctrl) { > + ret = regmap_update_bits(sc->regmap, sc->collapse_sleep_ctrl, mask, val ? mask : 0); > + if (ret) { > + regmap_update_bits(sc->regmap, reg, mask, val ? 0 : mask); > + return ret; > + } > + } > + Dimtry, based on our discussions with design, we understand that this is a one time setting and can be done from the Global clock controller probe. Thus, this patch can be dropped. /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ regmap_write(regmap, 0x62204, 0x0); > return 0; > } > > diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h > index 1e2779b823d1c8ca077c9b4cd0a0dbdf5f9457ef..dab2e31be8f65408d6d29df42ad5105830760d3e 100644 > --- a/drivers/clk/qcom/gdsc.h > +++ b/drivers/clk/qcom/gdsc.h > @@ -19,6 +19,7 @@ struct reset_controller_dev; > * @regmap: regmap for MMIO accesses > * @gdscr: gsdc control register > * @collapse_ctrl: APCS collapse-vote register > + * @collapse_sleep_ctrl: APCS collapse-vote register for the sleep state > * @collapse_mask: APCS collapse-vote mask > * @gds_hw_ctrl: gds_hw_ctrl register > * @cxcs: offsets of branch registers to toggle mem/periph bits in > @@ -37,6 +38,7 @@ struct gdsc { > struct regmap *regmap; > unsigned int gdscr; > unsigned int collapse_ctrl; > + unsigned int collapse_sleep_ctrl; > unsigned int collapse_mask; > unsigned int gds_hw_ctrl; > unsigned int clamp_io_ctrl; >
On Fri, Oct 18, 2024 at 03:58:25PM +0530, Taniya Das wrote: > > > On 10/17/2024 10:26 PM, Dmitry Baryshkov wrote: > > Some platforms use separate collapse vote registers for the active and > > sleep states. Extend gdsc_update_collapse_bit() to support separate > > collapse_sleep_ctrl register. > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > --- > > drivers/clk/qcom/gdsc.c | 8 ++++++++ > > drivers/clk/qcom/gdsc.h | 2 ++ > > 2 files changed, 10 insertions(+) > > > > diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c > > index fa5fe4c2a2ee7786c2e8858f3e41301f639e5d59..95f8e90a8d25673c8a97a03f92cbdad25c3259db 100644 > > --- a/drivers/clk/qcom/gdsc.c > > +++ b/drivers/clk/qcom/gdsc.c > > @@ -133,6 +133,14 @@ static int gdsc_update_collapse_bit(struct gdsc *sc, bool val) > > if (ret) > > return ret; > > + if (sc->collapse_sleep_ctrl) { > > + ret = regmap_update_bits(sc->regmap, sc->collapse_sleep_ctrl, mask, val ? mask : 0); > > + if (ret) { > > + regmap_update_bits(sc->regmap, reg, mask, val ? 0 : mask); > > + return ret; > > + } > > + } > > + > > Dimtry, based on our discussions with design, we understand that this is a > one time setting and can be done from the Global clock controller probe. > Thus, this patch can be dropped. Ack, thanks. I'll drop it from the next iteration. > > /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. > */ > regmap_write(regmap, 0x62204, 0x0); > > > return 0; > > } > > diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h > > index 1e2779b823d1c8ca077c9b4cd0a0dbdf5f9457ef..dab2e31be8f65408d6d29df42ad5105830760d3e 100644 > > --- a/drivers/clk/qcom/gdsc.h > > +++ b/drivers/clk/qcom/gdsc.h > > @@ -19,6 +19,7 @@ struct reset_controller_dev; > > * @regmap: regmap for MMIO accesses > > * @gdscr: gsdc control register > > * @collapse_ctrl: APCS collapse-vote register > > + * @collapse_sleep_ctrl: APCS collapse-vote register for the sleep state > > * @collapse_mask: APCS collapse-vote mask > > * @gds_hw_ctrl: gds_hw_ctrl register > > * @cxcs: offsets of branch registers to toggle mem/periph bits in > > @@ -37,6 +38,7 @@ struct gdsc { > > struct regmap *regmap; > > unsigned int gdscr; > > unsigned int collapse_ctrl; > > + unsigned int collapse_sleep_ctrl; > > unsigned int collapse_mask; > > unsigned int gds_hw_ctrl; > > unsigned int clamp_io_ctrl; > > > > -- > Thanks & Regards, > Taniya Das.
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index fa5fe4c2a2ee7786c2e8858f3e41301f639e5d59..95f8e90a8d25673c8a97a03f92cbdad25c3259db 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -133,6 +133,14 @@ static int gdsc_update_collapse_bit(struct gdsc *sc, bool val) if (ret) return ret; + if (sc->collapse_sleep_ctrl) { + ret = regmap_update_bits(sc->regmap, sc->collapse_sleep_ctrl, mask, val ? mask : 0); + if (ret) { + regmap_update_bits(sc->regmap, reg, mask, val ? 0 : mask); + return ret; + } + } + return 0; } diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 1e2779b823d1c8ca077c9b4cd0a0dbdf5f9457ef..dab2e31be8f65408d6d29df42ad5105830760d3e 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -19,6 +19,7 @@ struct reset_controller_dev; * @regmap: regmap for MMIO accesses * @gdscr: gsdc control register * @collapse_ctrl: APCS collapse-vote register + * @collapse_sleep_ctrl: APCS collapse-vote register for the sleep state * @collapse_mask: APCS collapse-vote mask * @gds_hw_ctrl: gds_hw_ctrl register * @cxcs: offsets of branch registers to toggle mem/periph bits in @@ -37,6 +38,7 @@ struct gdsc { struct regmap *regmap; unsigned int gdscr; unsigned int collapse_ctrl; + unsigned int collapse_sleep_ctrl; unsigned int collapse_mask; unsigned int gds_hw_ctrl; unsigned int clamp_io_ctrl;
Some platforms use separate collapse vote registers for the active and sleep states. Extend gdsc_update_collapse_bit() to support separate collapse_sleep_ctrl register. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gdsc.c | 8 ++++++++ drivers/clk/qcom/gdsc.h | 2 ++ 2 files changed, 10 insertions(+)