| Message ID | 20241016233044.240699-2-afd@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Use ti,j784s4-pcie-ctrl for PCIe CTRL spaces | expand |
On Wed, Oct 16, 2024 at 06:30:40PM -0500, Andrew Davis wrote: > Add a pattern property for pcie-ctrl which can be part of this controller. > > Signed-off-by: Andrew Davis <afd@ti.com> > --- > .../bindings/soc/ti/ti,j721e-system-controller.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml > index 378e9cc5fac2a..2a64fc61d1262 100644 > --- a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml > +++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml > @@ -68,6 +68,11 @@ patternProperties: > description: > The node corresponding to SoC chip identification. > > + "^pcie-ctrl@[0-9a-f]+$": > + type: object > + description: > + This is the PCIe control region. What goes in this node? > + > required: > - compatible > - reg > -- > 2.39.2 >
diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml index 378e9cc5fac2a..2a64fc61d1262 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml @@ -68,6 +68,11 @@ patternProperties: description: The node corresponding to SoC chip identification. + "^pcie-ctrl@[0-9a-f]+$": + type: object + description: + This is the PCIe control region. + required: - compatible - reg
Add a pattern property for pcie-ctrl which can be part of this controller. Signed-off-by: Andrew Davis <afd@ti.com> --- .../bindings/soc/ti/ti,j721e-system-controller.yaml | 5 +++++ 1 file changed, 5 insertions(+)