| Message ID | 20241022001134.828724-4-richard.henderson@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | tcg/riscv: Add support for vector | expand |
On 10/21/24 9:11 PM, Richard Henderson wrote: > From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com> > > Add support for probing RISC-V vector extension availability in > the backend. This information will be used when deciding whether > to use vector instructions in code generation. > > Cache lg2(vlenb) for the backend. The storing of lg2(vlenb) means > we can convert all of the division into subtraction. > > While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X, > we use RISCV_HWPROBE_IMA_V instead. RISCV_HWPROBE_IMA_V is more > strictly constrainted than RISCV_HWPROBE_EXT_ZVE64X. At least in > current QEMU implemenation, the V vector extension depends on the > zve64d extension. > > Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com> > Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> > Message-ID: <20241007025700.47259-2-zhiwei_liu@linux.alibaba.com> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- Tested with a KVM guest running in an emulated RV host. Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > host/include/riscv/host/cpuinfo.h | 2 ++ > util/cpuinfo-riscv.c | 34 ++++++++++++++++++++++++++++++- > 2 files changed, 35 insertions(+), 1 deletion(-) > > diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cpuinfo.h > index 2b00660e36..cdc784e7b6 100644 > --- a/host/include/riscv/host/cpuinfo.h > +++ b/host/include/riscv/host/cpuinfo.h > @@ -10,9 +10,11 @@ > #define CPUINFO_ZBA (1u << 1) > #define CPUINFO_ZBB (1u << 2) > #define CPUINFO_ZICOND (1u << 3) > +#define CPUINFO_ZVE64X (1u << 4) > > /* Initialized with a constructor. */ > extern unsigned cpuinfo; > +extern unsigned riscv_lg2_vlenb; > > /* > * We cannot rely on constructor ordering, so other constructors must > diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c > index 8cacc67645..971c924012 100644 > --- a/util/cpuinfo-riscv.c > +++ b/util/cpuinfo-riscv.c > @@ -4,6 +4,7 @@ > */ > > #include "qemu/osdep.h" > +#include "qemu/host-utils.h" > #include "host/cpuinfo.h" > > #ifdef CONFIG_ASM_HWPROBE_H > @@ -13,6 +14,7 @@ > #endif > > unsigned cpuinfo; > +unsigned riscv_lg2_vlenb; > static volatile sig_atomic_t got_sigill; > > static void sigill_handler(int signo, siginfo_t *si, void *data) > @@ -34,7 +36,7 @@ static void sigill_handler(int signo, siginfo_t *si, void *data) > /* Called both as constructor and (possibly) via other constructors. */ > unsigned __attribute__((constructor)) cpuinfo_init(void) > { > - unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND; > + unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND | CPUINFO_ZVE64X; > unsigned info = cpuinfo; > > if (info) { > @@ -50,6 +52,10 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) > #endif > #if defined(__riscv_arch_test) && defined(__riscv_zicond) > info |= CPUINFO_ZICOND; > +#endif > +#if defined(__riscv_arch_test) && \ > + (defined(__riscv_vector) || defined(__riscv_zve64x)) > + info |= CPUINFO_ZVE64X; > #endif > left &= ~info; > > @@ -69,11 +75,22 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) > #ifdef RISCV_HWPROBE_EXT_ZICOND > info |= pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICOND : 0; > left &= ~CPUINFO_ZICOND; > +#endif > + /* For rv64, V is Zve64d, a superset of Zve64x. */ > + info |= pair.value & RISCV_HWPROBE_IMA_V ? CPUINFO_ZVE64X : 0; > +#ifdef RISCV_HWPROBE_EXT_ZVE64X > + info |= pair.value & RISCV_HWPROBE_EXT_ZVE64X ? CPUINFO_ZVE64X : 0; > #endif > } > } > #endif /* CONFIG_ASM_HWPROBE_H */ > > + /* > + * We only detect support for vectors with hwprobe. All kernels with > + * support for vectors in userspace also support the hwprobe syscall. > + */ > + left &= ~CPUINFO_ZVE64X; > + > if (left) { > struct sigaction sa_old, sa_new; > > @@ -113,6 +130,21 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) > assert(left == 0); > } > > + if (info & CPUINFO_ZVE64X) { > + /* > + * We are guaranteed by RVV-1.0 that VLEN is a power of 2. > + * We are guaranteed by Zve64x that VLEN >= 64, and that > + * EEW of {8,16,32,64} are supported. > + */ > + unsigned long vlenb; > + /* csrr %0, vlenb */ > + asm volatile(".insn i 0x73, 0x2, %0, zero, -990" : "=r"(vlenb)); > + assert(vlenb >= 8); > + assert(is_power_of_2(vlenb)); > + /* Cache VLEN in a convenient form. */ > + riscv_lg2_vlenb = ctz32(vlenb); > + } > + > info |= CPUINFO_ALWAYS; > cpuinfo = info; > return info;
diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cpuinfo.h index 2b00660e36..cdc784e7b6 100644 --- a/host/include/riscv/host/cpuinfo.h +++ b/host/include/riscv/host/cpuinfo.h @@ -10,9 +10,11 @@ #define CPUINFO_ZBA (1u << 1) #define CPUINFO_ZBB (1u << 2) #define CPUINFO_ZICOND (1u << 3) +#define CPUINFO_ZVE64X (1u << 4) /* Initialized with a constructor. */ extern unsigned cpuinfo; +extern unsigned riscv_lg2_vlenb; /* * We cannot rely on constructor ordering, so other constructors must diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c index 8cacc67645..971c924012 100644 --- a/util/cpuinfo-riscv.c +++ b/util/cpuinfo-riscv.c @@ -4,6 +4,7 @@ */ #include "qemu/osdep.h" +#include "qemu/host-utils.h" #include "host/cpuinfo.h" #ifdef CONFIG_ASM_HWPROBE_H @@ -13,6 +14,7 @@ #endif unsigned cpuinfo; +unsigned riscv_lg2_vlenb; static volatile sig_atomic_t got_sigill; static void sigill_handler(int signo, siginfo_t *si, void *data) @@ -34,7 +36,7 @@ static void sigill_handler(int signo, siginfo_t *si, void *data) /* Called both as constructor and (possibly) via other constructors. */ unsigned __attribute__((constructor)) cpuinfo_init(void) { - unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND; + unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND | CPUINFO_ZVE64X; unsigned info = cpuinfo; if (info) { @@ -50,6 +52,10 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) #endif #if defined(__riscv_arch_test) && defined(__riscv_zicond) info |= CPUINFO_ZICOND; +#endif +#if defined(__riscv_arch_test) && \ + (defined(__riscv_vector) || defined(__riscv_zve64x)) + info |= CPUINFO_ZVE64X; #endif left &= ~info; @@ -69,11 +75,22 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) #ifdef RISCV_HWPROBE_EXT_ZICOND info |= pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICOND : 0; left &= ~CPUINFO_ZICOND; +#endif + /* For rv64, V is Zve64d, a superset of Zve64x. */ + info |= pair.value & RISCV_HWPROBE_IMA_V ? CPUINFO_ZVE64X : 0; +#ifdef RISCV_HWPROBE_EXT_ZVE64X + info |= pair.value & RISCV_HWPROBE_EXT_ZVE64X ? CPUINFO_ZVE64X : 0; #endif } } #endif /* CONFIG_ASM_HWPROBE_H */ + /* + * We only detect support for vectors with hwprobe. All kernels with + * support for vectors in userspace also support the hwprobe syscall. + */ + left &= ~CPUINFO_ZVE64X; + if (left) { struct sigaction sa_old, sa_new; @@ -113,6 +130,21 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) assert(left == 0); } + if (info & CPUINFO_ZVE64X) { + /* + * We are guaranteed by RVV-1.0 that VLEN is a power of 2. + * We are guaranteed by Zve64x that VLEN >= 64, and that + * EEW of {8,16,32,64} are supported. + */ + unsigned long vlenb; + /* csrr %0, vlenb */ + asm volatile(".insn i 0x73, 0x2, %0, zero, -990" : "=r"(vlenb)); + assert(vlenb >= 8); + assert(is_power_of_2(vlenb)); + /* Cache VLEN in a convenient form. */ + riscv_lg2_vlenb = ctz32(vlenb); + } + info |= CPUINFO_ALWAYS; cpuinfo = info; return info;