| Message ID | 20241022004710.1888067-1-rananta@google.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Fix arm64 clang errors on fpu tests | expand |
On Tue, Oct 22, 2024 at 12:47:07AM +0000, Raghavendra Rao Ananta wrote: > When compiled with clang for arm64, some build errors were observed > along the fpu code. Moreover, data aborts were seen while running > the arm/fpu test due to misconfigured input/output args in the inline > assembly. > > The series tries to addresses these issues. > > - Raghavendra > > Raghavendra Rao Ananta (3): > arm: Fix clang error in sve_vl() > arm: fpu: Convert 'q' registers to 'v' to satisfy clang > arm: fpu: Fix the input/output args for inline asm in fpu.c > > arm/fpu.c | 46 +++++++++++++++++++-------------------- > lib/arm64/asm/processor.h | 2 +- > 2 files changed, 24 insertions(+), 24 deletions(-) > > > base-commit: f246b16099478a916eab37b9bd1eb07c743a67d5 > -- > 2.47.0.105.g07ac214952-goog > Hi Raghavendra, With clang 18.1.8 (Fedora 18.1.8-1.fc40) I get a bunch of errors like these arm/fpu.c:281:3: error: instruction requires: fp-armv8 I used my cross-clang series[1] and configured with ./configure --arch=arm64 --cc=clang --cflags='--target=aarch64' --cross-prefix=aarch64-linux-gnu- [1] https://lore.kernel.org/all/20240911091406.134240-7-andrew.jones@linux.dev/ Thanks, drew
Hi Andrew, On Tue, Oct 22, 2024 at 6:10 AM Andrew Jones <andrew.jones@linux.dev> wrote: > > With clang 18.1.8 (Fedora 18.1.8-1.fc40) I get a bunch of errors like > these > > arm/fpu.c:281:3: error: instruction requires: fp-armv8 > > I used my cross-clang series[1] and configured with > > ./configure --arch=arm64 --cc=clang --cflags='--target=aarch64' --cross-prefix=aarch64-linux-gnu- > > [1] https://lore.kernel.org/all/20240911091406.134240-7-andrew.jones@linux.dev/ > > Thanks, > drew I was able to reproduce the errors by pointing to a newer clang (20) and applying your series. I think we see the errors because llvm decided to disable loads and stores on FP registers with "-mgeneral-regs-only" [1]. Explicitly adding ".arch_extension fp" for the fp_reg_{read,write}() helped with the build: diff --git a/arm/fpu.c b/arm/fpu.c index 6b0411d3..f44ed82a 100644 --- a/arm/fpu.c +++ b/arm/fpu.c @@ -38,7 +38,8 @@ static inline bool arch_collect_entropy(uint64_t *random) #define fpu_reg_read(val) \ ({ \ uint64_t *__val = (val); \ - asm volatile("stp q0, q1, [%0], #32\n\t" \ + asm volatile(".arch_extension fp\n" \ + "stp q0, q1, [%0], #32\n\t" \ "stp q2, q3, [%0], #32\n\t" \ "stp q4, q5, [%0], #32\n\t" \ "stp q6, q7, [%0], #32\n\t" \ @@ -71,7 +72,8 @@ static inline bool arch_collect_entropy(uint64_t *random) #define fpu_reg_write(val) \ do { \ uint64_t *__val = (val); \ - asm volatile("ldp q0, q1, [%0], #32\n\t" \ + asm volatile(".arch_extension fp\n" \ + "ldp q0, q1, [%0], #32\n\t" \ "ldp q2, q3, [%0], #32\n\t" \ "ldp q4, q5, [%0], #32\n\t" \ "ldp q6, q7, [%0], #32\n\t" \ If you are fine with this, I can push it as a separate patch in v2. Thank you. Raghavendra [1]: https://github.com/llvm/llvm-project/pull/77817
On Tue, Oct 22, 2024 at 01:31:24PM -0700, Raghavendra Rao Ananta wrote: > Hi Andrew, > > > > > With clang 18.1.8 (Fedora 18.1.8-1.fc40) I get a bunch of errors like > > these > > > > arm/fpu.c:281:3: error: instruction requires: fp-armv8 > > > > I used my cross-clang series[1] and configured with > > > > ./configure --arch=arm64 --cc=clang --cflags='--target=aarch64' > --cross-prefix=aarch64-linux-gnu- > > > > [1] > https://lore.kernel.org/all/20240911091406.134240-7-andrew.jones@linux.dev/ > > > > Thanks, > > drew > > I was able to reproduce the errors by pointing to a newer clang (20) and > applying your series. > I think we see the errors because llvm decided to disable loads and stores > on FP registers with "-mgeneral-regs-only" [1]. Explicitly adding > ".arch_extension fp" for the fp_reg_{read,write}() helped with the build: > > diff --git a/arm/fpu.c b/arm/fpu.c > index 6b0411d3..f44ed82a 100644 > --- a/arm/fpu.c > +++ b/arm/fpu.c > @@ -38,7 +38,8 @@ static inline bool arch_collect_entropy(uint64_t *random) > #define fpu_reg_read(val) \ > ({ \ > uint64_t *__val = (val); \ > - asm volatile("stp q0, q1, [%0], #32\n\t" \ > + asm volatile(".arch_extension fp\n" \ > + "stp q0, q1, [%0], #32\n\t" \ > "stp q2, q3, [%0], #32\n\t" \ > "stp q4, q5, [%0], #32\n\t" \ > "stp q6, q7, [%0], #32\n\t" \ > @@ -71,7 +72,8 @@ static inline bool arch_collect_entropy(uint64_t *random) > #define fpu_reg_write(val) \ > do { \ > uint64_t *__val = (val); \ > - asm volatile("ldp q0, q1, [%0], #32\n\t" \ > + asm volatile(".arch_extension fp\n" \ > + "ldp q0, q1, [%0], #32\n\t" \ > "ldp q2, q3, [%0], #32\n\t" \ > "ldp q4, q5, [%0], #32\n\t" \ > "ldp q6, q7, [%0], #32\n\t" \ > > If you are fine with this, I can push it as a separate patch in v2. The fix works for me too. Please post v2. Thanks, drew