| Message ID | 20241023065257.190035-5-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for 3 VDSC engines 12 slices | expand |
> -----Original Message----- > From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com> > Sent: Wednesday, October 23, 2024 12:23 PM > To: intel-gfx@lists.freedesktop.org > Cc: intel-xe@lists.freedesktop.org; Kandpal, Suraj <suraj.kandpal@intel.com> > Subject: [PATCH 04/16] drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2 > > Introduce the register bits to enable the 3rd DSC engine VDSC2. > Add support to read/write these bits. > > v2: Only introduce bits that are used and update the subject and commit > message. (Suraj) > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> LGTM, Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +++++++++- > drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 2 ++ > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c > b/drivers/gpu/drm/i915/display/intel_vdsc.c > index 159f83edd5b0..29b1aa7f4f94 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -775,6 +775,12 @@ void intel_dsc_enable(const struct intel_crtc_state > *crtc_state) > dss_ctl2_val |= VDSC1_ENABLE; > dss_ctl1_val |= JOINER_ENABLE; > } > + > + if (vdsc_instances_per_pipe > 2) { > + dss_ctl2_val |= VDSC2_ENABLE; > + dss_ctl2_val |= SMALL_JOINER_CONFIG_3_ENGINES; > + } > + > if (crtc_state->joiner_pipes) { > if (intel_crtc_ultrajoiner_enable_needed(crtc_state)) > dss_ctl1_val |= ULTRA_JOINER_ENABLE; @@ -977,7 > +983,9 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) > goto out; > > if (dss_ctl1 & JOINER_ENABLE) { > - if (dss_ctl2 & VDSC1_ENABLE) > + if (dss_ctl2 & (VDSC2_ENABLE | > SMALL_JOINER_CONFIG_3_ENGINES)) > + crtc_state->dsc.num_streams = 3; > + else if (dss_ctl2 & VDSC1_ENABLE) > crtc_state->dsc.num_streams = 2; > else > crtc_state->dsc.num_streams = 1; > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h > b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h > index d7a72b95ee7e..474a7f9f3881 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h > @@ -22,6 +22,8 @@ > > #define DSS_CTL2 _MMIO(0x67404) > #define VDSC0_ENABLE REG_BIT(31) > +#define VDSC2_ENABLE REG_BIT(30) > +#define SMALL_JOINER_CONFIG_3_ENGINES REG_BIT(23) > #define VDSC1_ENABLE REG_BIT(15) > #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) > #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) > -- > 2.45.2
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 159f83edd5b0..29b1aa7f4f94 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -775,6 +775,12 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) dss_ctl2_val |= VDSC1_ENABLE; dss_ctl1_val |= JOINER_ENABLE; } + + if (vdsc_instances_per_pipe > 2) { + dss_ctl2_val |= VDSC2_ENABLE; + dss_ctl2_val |= SMALL_JOINER_CONFIG_3_ENGINES; + } + if (crtc_state->joiner_pipes) { if (intel_crtc_ultrajoiner_enable_needed(crtc_state)) dss_ctl1_val |= ULTRA_JOINER_ENABLE; @@ -977,7 +983,9 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) goto out; if (dss_ctl1 & JOINER_ENABLE) { - if (dss_ctl2 & VDSC1_ENABLE) + if (dss_ctl2 & (VDSC2_ENABLE | SMALL_JOINER_CONFIG_3_ENGINES)) + crtc_state->dsc.num_streams = 3; + else if (dss_ctl2 & VDSC1_ENABLE) crtc_state->dsc.num_streams = 2; else crtc_state->dsc.num_streams = 1; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index d7a72b95ee7e..474a7f9f3881 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -22,6 +22,8 @@ #define DSS_CTL2 _MMIO(0x67404) #define VDSC0_ENABLE REG_BIT(31) +#define VDSC2_ENABLE REG_BIT(30) +#define SMALL_JOINER_CONFIG_3_ENGINES REG_BIT(23) #define VDSC1_ENABLE REG_BIT(15) #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
Introduce the register bits to enable the 3rd DSC engine VDSC2. Add support to read/write these bits. v2: Only introduce bits that are used and update the subject and commit message. (Suraj) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +++++++++- drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-)