| Message ID | 20241023145345.1613824-13-maz@kernel.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | KVM: arm64: Add EL2 support to FEAT_S1PIE/S1POE | expand |
On Wed, Oct 23, 2024 at 03:53:20PM +0100, Marc Zyngier wrote: > TCR2_EL2 is a bag of control bits, all of which are only valid if > certain features are present, and RES0 otherwise. > > Describe these constraints and register them with the masking > infrastructure. > > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > arch/arm64/kvm/nested.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c > index b20b3bfb9caec..b4b3ec88399b3 100644 > --- a/arch/arm64/kvm/nested.c > +++ b/arch/arm64/kvm/nested.c > @@ -1179,6 +1179,28 @@ int kvm_init_nv_sysregs(struct kvm *kvm) > res0 |= ~(res0 | res1); > set_sysreg_masks(kvm, HAFGRTR_EL2, res0, res1); > > + /* TCR2_EL2 */ > + res0 = TCR2_EL2_RES0; > + res1 = TCR2_EL2_RES1; > + if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, D128, IMP)) > + res0 |= (TCR2_EL2_DisCH0 | TCR2_EL2_DisCH1 | TCR2_EL2_D128); > + if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, MEC, IMP)) > + res0 |= TCR2_EL2_AMEC1 | TCR2_EL2_AMEC0; > + if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, HAFDBS, HAFT)) > + res0 |= TCR2_EL2_HAFT; > + if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, THE, IMP)) > + res0 |= TCR2_EL2_PTTWI | TCR2_EL2_PnCH; > + if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, AIE, IMP)) > + res0 |= TCR2_EL2_AIE; > + if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1POE, IMP)) > + res0 |= TCR2_EL2_POE | TCR2_EL2_E0POE; > + if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1PIE, IMP)) > + res0 |= TCR2_EL2_PIE; > + if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, VH, IMP)) > + res0 |= (TCR2_EL2_E0POE | TCR2_EL2_D128 | > + TCR2_EL2_AMEC1 | TCR2_EL2_DisCH0 | TCR2_EL2_DisCH1); > + set_sysreg_masks(kvm, TCR2_EL2, res0, res1); > + > /* SCTLR_EL1 */ > res0 = SCTLR_EL1_RES0; > res1 = SCTLR_EL1_RES1; Reviewed-by: Joey Gouly <joey.gouly@arm.com>
diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index b20b3bfb9caec..b4b3ec88399b3 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -1179,6 +1179,28 @@ int kvm_init_nv_sysregs(struct kvm *kvm) res0 |= ~(res0 | res1); set_sysreg_masks(kvm, HAFGRTR_EL2, res0, res1); + /* TCR2_EL2 */ + res0 = TCR2_EL2_RES0; + res1 = TCR2_EL2_RES1; + if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, D128, IMP)) + res0 |= (TCR2_EL2_DisCH0 | TCR2_EL2_DisCH1 | TCR2_EL2_D128); + if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, MEC, IMP)) + res0 |= TCR2_EL2_AMEC1 | TCR2_EL2_AMEC0; + if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, HAFDBS, HAFT)) + res0 |= TCR2_EL2_HAFT; + if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, THE, IMP)) + res0 |= TCR2_EL2_PTTWI | TCR2_EL2_PnCH; + if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, AIE, IMP)) + res0 |= TCR2_EL2_AIE; + if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1POE, IMP)) + res0 |= TCR2_EL2_POE | TCR2_EL2_E0POE; + if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1PIE, IMP)) + res0 |= TCR2_EL2_PIE; + if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, VH, IMP)) + res0 |= (TCR2_EL2_E0POE | TCR2_EL2_D128 | + TCR2_EL2_AMEC1 | TCR2_EL2_DisCH0 | TCR2_EL2_DisCH1); + set_sysreg_masks(kvm, TCR2_EL2, res0, res1); + /* SCTLR_EL1 */ res0 = SCTLR_EL1_RES0; res1 = SCTLR_EL1_RES1;
TCR2_EL2 is a bag of control bits, all of which are only valid if certain features are present, and RES0 otherwise. Describe these constraints and register them with the masking infrastructure. Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/kvm/nested.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)