| Message ID | 20241023214701.963830-5-clinton.a.taylor@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/xe3lpd: ptl display patches | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Clint > Taylor > Sent: 24 October 2024 03:17 > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org > Subject: [PATCH v2 04/12] drm/i915/display/ptl: Fill VRR crtc_state timings > before other transcoder timings > > From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> > > In progress to make VRR timing generator as the default timing generator, > rest other timings will be derived based on vrr.vmin and vrr.vmax. Call > intel_vrr_get_config before intel_get_transcoder_timings to accommodate > values getting pre-filled. > > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index ef1436146325..01466611eebe 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -4134,13 +4134,13 @@ static bool hsw_get_pipe_config(struct intel_crtc > *crtc, > intel_joiner_get_config(pipe_config); > intel_dsc_get_config(pipe_config); > > + if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config- > >cpu_transcoder)) > + intel_vrr_get_config(pipe_config); > + > if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || > DISPLAY_VER(dev_priv) >= 11) > intel_get_transcoder_timings(crtc, pipe_config); > > - if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config- > >cpu_transcoder)) > - intel_vrr_get_config(pipe_config); > - Hi @Clint Taylor ref: https://patchwork.freedesktop.org/patch/620416/?series=140195&rev=1 As I have mentioned on revision 1, this patch does not have any significance as stand alone, we will be adding this patch as part of Ankit Nautiyal's VRR default timing generator patch series which is under progress. For now we can drop this patch from this series, This single patch does not have impact even if added here. Regards, Mitul > intel_get_pipe_src_size(crtc, pipe_config); > > if (IS_HASWELL(dev_priv)) { > -- > 2.25.1
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ef1436146325..01466611eebe 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4134,13 +4134,13 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, intel_joiner_get_config(pipe_config); intel_dsc_get_config(pipe_config); + if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) + intel_vrr_get_config(pipe_config); + if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || DISPLAY_VER(dev_priv) >= 11) intel_get_transcoder_timings(crtc, pipe_config); - if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) - intel_vrr_get_config(pipe_config); - intel_get_pipe_src_size(crtc, pipe_config); if (IS_HASWELL(dev_priv)) {