| Message ID | 20241024035552.94363-5-suraj.kandpal@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add 6k resolution support for a single CRTC | expand |
On 10/24/2024 9:25 AM, Suraj Kandpal wrote: > We only support resolution up to 4k for single pipe when using > YUV420 format so we prune these modes and restrict the plane size > at src. This applies from MTL+ onwards, where the scaler can handle horizontal source sizes up to 4096 (Bspec: 50441). Prior platforms support horizontal source sizes up to 5120. For YCBCR420-only mode, a scaler is required to downsample 444 to 420 before sending to the sink. If there is a mode with hactive > 4096, this creates a problem, so pruning such modes is necessary for the platforms that have the above restriction. However, if a PCON is present and can support 444 to 420 conversion, we can still display the mode by configuring the PCON for this conversion. So need to capture the above reasoning, and prune such modes, if its not a branch device or if pcon doesnt support 444-420 conversion. Regards, Ankit > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index e0baad468d76..edaea5e8c53c 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1373,6 +1373,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, > { > struct intel_connector *connector = to_intel_connector(_connector); > struct intel_dp *intel_dp = intel_attached_dp(connector); > + enum intel_output_format sink_format; > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > const struct drm_display_mode *fixed_mode; > int target_clock = mode->clock; > @@ -1407,6 +1408,11 @@ intel_dp_mode_valid(struct drm_connector *_connector, > mode->hdisplay, target_clock); > max_dotclk *= num_joined_pipes; > > + sink_format = intel_dp_sink_format(connector, mode); > + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 && > + mode->hdisplay > 4096) > + return MODE_NO_420; > + > if (target_clock > max_dotclk) > return MODE_CLOCK_HIGH; >
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index e0baad468d76..edaea5e8c53c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1373,6 +1373,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, { struct intel_connector *connector = to_intel_connector(_connector); struct intel_dp *intel_dp = intel_attached_dp(connector); + enum intel_output_format sink_format; struct drm_i915_private *dev_priv = to_i915(connector->base.dev); const struct drm_display_mode *fixed_mode; int target_clock = mode->clock; @@ -1407,6 +1408,11 @@ intel_dp_mode_valid(struct drm_connector *_connector, mode->hdisplay, target_clock); max_dotclk *= num_joined_pipes; + sink_format = intel_dp_sink_format(connector, mode); + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 && + mode->hdisplay > 4096) + return MODE_NO_420; + if (target_clock > max_dotclk) return MODE_CLOCK_HIGH;
We only support resolution up to 4k for single pipe when using YUV420 format so we prune these modes and restrict the plane size at src. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++ 1 file changed, 6 insertions(+)