| Message ID | 20241023145345.1613824-18-maz@kernel.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | KVM: arm64: Add EL2 support to FEAT_S1PIE/S1POE | expand |
On Wed, Oct 23, 2024 at 03:53:25PM +0100, Marc Zyngier wrote: > Add the missing sanitisation of ID_AA64MMFR3_EL1, making sure we > solely expose S1PIE and TCRX (we currently don't support anything > else). > case SYS_ID_AA64MMFR3_EL1: > - val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE; > + > + val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE | > + ID_AA64MMFR3_EL1_S1PIE; The changelog is now out of date, POE has been added.
On Thu, Oct 24, 2024 at 01:32:09PM +0100, Mark Brown wrote: > On Wed, Oct 23, 2024 at 03:53:25PM +0100, Marc Zyngier wrote: > > > Add the missing sanitisation of ID_AA64MMFR3_EL1, making sure we > > solely expose S1PIE and TCRX (we currently don't support anything > > else). > > > case SYS_ID_AA64MMFR3_EL1: > > - val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE; > > + > > + val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE | > > + ID_AA64MMFR3_EL1_S1PIE; > > The changelog is now out of date, POE has been added. This will disappear with a rebase won't it? Since you made the same change in d4a89e5aee23 ("KVM: arm64: Expose S1PIE to guests"), in Linus' tree. Thanks, Joey
On Thu, Oct 24, 2024 at 01:45:28PM +0100, Joey Gouly wrote: > On Thu, Oct 24, 2024 at 01:32:09PM +0100, Mark Brown wrote: > > The changelog is now out of date, POE has been added. > This will disappear with a rebase won't it? Since you made the same change in > d4a89e5aee23 ("KVM: arm64: Expose S1PIE to guests"), in Linus' tree. Yeah, it should go away if the code is rebased.
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c42f09a67a7c9..c9638541c0994 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1617,7 +1617,9 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; break; case SYS_ID_AA64MMFR3_EL1: - val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE; + + val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE | + ID_AA64MMFR3_EL1_S1PIE; break; case SYS_ID_MMFR4_EL1: val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); @@ -2500,7 +2502,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_AA64MMFR2_EL1_NV | ID_AA64MMFR2_EL1_CCIDX)), ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | - ID_AA64MMFR3_EL1_S1POE)), + ID_AA64MMFR3_EL1_S1POE | + ID_AA64MMFR3_EL1_S1PIE)), ID_SANITISED(ID_AA64MMFR4_EL1), ID_UNALLOCATED(7,5), ID_UNALLOCATED(7,6),
Add the missing sanitisation of ID_AA64MMFR3_EL1, making sure we solely expose S1PIE and TCRX (we currently don't support anything else). Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/kvm/sys_regs.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)