| Message ID | 20241021-wip-bl-ad3552r-axi-v0-iio-testing-v7-2-969694f53c5d@baylibre.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | iio: add support for the ad3552r AXI DAC IP | expand |
On Mon, Oct 21, 2024 at 02:40:12PM +0200, Angelo Dureghello wrote: > From: Angelo Dureghello <adureghello@baylibre.com> > > Add a new compatible and related bindigns for the fpga-based > "ad3552r" AXI IP core, a variant of the generic AXI DAC IP. > > The AXI "ad3552r" IP is a very similar HDL (fpga) variant of the > generic AXI "DAC" IP, intended to control ad3552r and similar chips, > mainly to reach high speed transfer rates using a QSPI DDR > (dobule-data-rate) interface. > > The ad3552r device is defined as a child of the AXI DAC, that in > this case is acting as an SPI controller. > > Note, #io-backend is present because it is possible (in theory anyway) > to use a separate controller for the control path than that used > for the datapath. > > Signed-off-by: Angelo Dureghello <adureghello@baylibre.com> > --- > .../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 69 +++++++++++++++++++++- > 1 file changed, 66 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > index a55e9bfc66d7..0aabb210f26d 100644 > --- a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > @@ -19,11 +19,13 @@ description: | > memory via DMA into the DAC. > > https://wiki.analog.com/resources/fpga/docs/axi_dac_ip > + https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html > > properties: > compatible: > enum: > - adi,axi-dac-9.1.b > + - adi,axi-ad3552r > > reg: > maxItems: 1 > @@ -36,7 +38,12 @@ properties: > - const: tx > > clocks: > - maxItems: 1 > + minItems: 1 > + maxItems: 2 > + > + clock-names: > + minItems: 1 > + maxItems: 2 > > '#io-backend-cells': > const: 0 > @@ -47,7 +54,31 @@ required: > - reg > - clocks > > -additionalProperties: false > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: adi,axi-ad3552r > + then: > + $ref: /schemas/spi/spi-controller.yaml# > + properties: > + clocks: > + minItems: 2 > + maxItems: 2 Is this maxItems required? It matches the outer maximum. > + clock-names: > + items: > + - const: s_axi_aclk > + - const: dac_clk The names are the same in both cases, you can move the definitions outside of the if/then/else stuff and only constrain it here. > + else: > + properties: > + clocks: > + maxItems: 1 > + clock-names: > + items: > + - const: s_axi_aclk > + > +unevaluatedProperties: false > > examples: > - | > @@ -57,6 +88,38 @@ examples: > dmas = <&tx_dma 0>; > dma-names = "tx"; > #io-backend-cells = <0>; > - clocks = <&axi_clk>; > + clocks = <&clkc 15>; > + clock-names = "s_axi_aclk"; > + }; > + > + - | > + #include <dt-bindings/gpio/gpio.h> > + axi_dac: spi@44a70000 { > + compatible = "adi,axi-ad3552r"; > + reg = <0x44a70000 0x1000>; > + dmas = <&dac_tx_dma 0>; > + dma-names = "tx"; > + #io-backend-cells = <0>; > + clocks = <&clkc 15>, <&ref_clk>; > + clock-names = "s_axi_aclk", "dac_clk"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + dac@0 { > + compatible = "adi,ad3552r"; > + reg = <0>; > + reset-gpios = <&gpio0 92 GPIO_ACTIVE_HIGH>; > + io-backends = <&axi_dac>; > + spi-max-frequency = <20000000>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + channel@0 { > + reg = <0>; > + adi,output-range-microvolt = <(-10000000) (10000000)>; > + }; > + }; > }; > ... > > -- > 2.45.0.rc1 >
Hi Conor, On 22.10.2024 18:22, Conor Dooley wrote: > On Mon, Oct 21, 2024 at 02:40:12PM +0200, Angelo Dureghello wrote: > > From: Angelo Dureghello <adureghello@baylibre.com> > > > > Add a new compatible and related bindigns for the fpga-based > > "ad3552r" AXI IP core, a variant of the generic AXI DAC IP. > > > > The AXI "ad3552r" IP is a very similar HDL (fpga) variant of the > > generic AXI "DAC" IP, intended to control ad3552r and similar chips, > > mainly to reach high speed transfer rates using a QSPI DDR > > (dobule-data-rate) interface. > > > > The ad3552r device is defined as a child of the AXI DAC, that in > > this case is acting as an SPI controller. > > > > Note, #io-backend is present because it is possible (in theory anyway) > > to use a separate controller for the control path than that used > > for the datapath. > > > > Signed-off-by: Angelo Dureghello <adureghello@baylibre.com> > > --- > > .../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 69 +++++++++++++++++++++- > > 1 file changed, 66 insertions(+), 3 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > index a55e9bfc66d7..0aabb210f26d 100644 > > --- a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > @@ -19,11 +19,13 @@ description: | > > memory via DMA into the DAC. > > > > https://wiki.analog.com/resources/fpga/docs/axi_dac_ip > > + https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html > > > > properties: > > compatible: > > enum: > > - adi,axi-dac-9.1.b > > + - adi,axi-ad3552r > > > > reg: > > maxItems: 1 > > @@ -36,7 +38,12 @@ properties: > > - const: tx > > > > clocks: > > - maxItems: 1 > > + minItems: 1 > > + maxItems: 2 > > + > > + clock-names: > > + minItems: 1 > > + maxItems: 2 > > > > '#io-backend-cells': > > const: 0 > > @@ -47,7 +54,31 @@ required: > > - reg > > - clocks > > > > -additionalProperties: false > > +allOf: > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: adi,axi-ad3552r > > + then: > > + $ref: /schemas/spi/spi-controller.yaml# > > + properties: > > + clocks: > > + minItems: 2 > > + maxItems: 2 > > Is this maxItems required? It matches the outer maximum. > > > + clock-names: > > + items: > > + - const: s_axi_aclk > > + - const: dac_clk > > The names are the same in both cases, you can move the definitions > outside of the if/then/else stuff and only constrain it here. > thanks, could you maybe have a look if it's ok now ? (maxItems not needed for a const list) clocks: minItems: 1 maxItems: 2 clock-names: items: - const: s_axi_aclk - const: dac_clk minItems: 1 '#io-backend-cells': const: 0 required: - compatible - dmas - reg - clocks allOf: - if: properties: compatible: contains: const: adi,axi-ad3552r then: $ref: /schemas/spi/spi-controller.yaml# properties: clocks: minItems: 2 clock-names: minItems: 2 else: properties: clocks: maxItems: 1 clock-names: maxItems: 1 unevaluatedProperties: false ... > > + else: > > + properties: > > + clocks: > > + maxItems: 1 > > + clock-names: > > + items: > > + - const: s_axi_aclk > > + > > +unevaluatedProperties: false > > > > examples: > > - | > > @@ -57,6 +88,38 @@ examples: > > dmas = <&tx_dma 0>; > > dma-names = "tx"; > > #io-backend-cells = <0>; > > - clocks = <&axi_clk>; > > + clocks = <&clkc 15>; > > + clock-names = "s_axi_aclk"; > > + }; > > + > > + - | > > + #include <dt-bindings/gpio/gpio.h> > > + axi_dac: spi@44a70000 { > > + compatible = "adi,axi-ad3552r"; > > + reg = <0x44a70000 0x1000>; > > + dmas = <&dac_tx_dma 0>; > > + dma-names = "tx"; > > + #io-backend-cells = <0>; > > + clocks = <&clkc 15>, <&ref_clk>; > > + clock-names = "s_axi_aclk", "dac_clk"; > > + > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + dac@0 { > > + compatible = "adi,ad3552r"; > > + reg = <0>; > > + reset-gpios = <&gpio0 92 GPIO_ACTIVE_HIGH>; > > + io-backends = <&axi_dac>; > > + spi-max-frequency = <20000000>; > > + > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + channel@0 { > > + reg = <0>; > > + adi,output-range-microvolt = <(-10000000) (10000000)>; > > + }; > > + }; > > }; > > ... > > > > -- > > 2.45.0.rc1 > >
On Thu, 2024-10-24 at 11:28 +0200, Angelo Dureghello wrote: > Hi Conor, > > On 22.10.2024 18:22, Conor Dooley wrote: > > On Mon, Oct 21, 2024 at 02:40:12PM +0200, Angelo Dureghello wrote: > > > From: Angelo Dureghello <adureghello@baylibre.com> > > > > > > Add a new compatible and related bindigns for the fpga-based > > > "ad3552r" AXI IP core, a variant of the generic AXI DAC IP. > > > > > > The AXI "ad3552r" IP is a very similar HDL (fpga) variant of the > > > generic AXI "DAC" IP, intended to control ad3552r and similar chips, > > > mainly to reach high speed transfer rates using a QSPI DDR > > > (dobule-data-rate) interface. > > > > > > The ad3552r device is defined as a child of the AXI DAC, that in > > > this case is acting as an SPI controller. > > > > > > Note, #io-backend is present because it is possible (in theory anyway) > > > to use a separate controller for the control path than that used > > > for the datapath. > > > > > > Signed-off-by: Angelo Dureghello <adureghello@baylibre.com> > > > --- > > > .../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 69 +++++++++++++++++++++- > > > 1 file changed, 66 insertions(+), 3 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > > b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > > index a55e9bfc66d7..0aabb210f26d 100644 > > > --- a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > > +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > > @@ -19,11 +19,13 @@ description: | > > > memory via DMA into the DAC. > > > > > > https://wiki.analog.com/resources/fpga/docs/axi_dac_ip > > > + https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html > > > > > > properties: > > > compatible: > > > enum: > > > - adi,axi-dac-9.1.b > > > + - adi,axi-ad3552r > > > > > > reg: > > > maxItems: 1 > > > @@ -36,7 +38,12 @@ properties: > > > - const: tx > > > > > > clocks: > > > - maxItems: 1 > > > + minItems: 1 > > > + maxItems: 2 > > > + > > > + clock-names: > > > + minItems: 1 > > > + maxItems: 2 > > > > > > '#io-backend-cells': > > > const: 0 > > > @@ -47,7 +54,31 @@ required: > > > - reg > > > - clocks > > > > > > -additionalProperties: false > > > +allOf: > > > + - if: > > > + properties: > > > + compatible: > > > + contains: > > > + const: adi,axi-ad3552r > > > + then: > > > + $ref: /schemas/spi/spi-controller.yaml# > > > + properties: > > > + clocks: > > > + minItems: 2 > > > + maxItems: 2 > > > > Is this maxItems required? It matches the outer maximum. > > > > > + clock-names: > > > + items: > > > + - const: s_axi_aclk > > > + - const: dac_clk > > > > The names are the same in both cases, you can move the definitions > > outside of the if/then/else stuff and only constrain it here. > > > thanks, could you maybe have a look if it's ok now ? > (maxItems not needed for a const list) > > clocks: > minItems: 1 > maxItems: 2 > > clock-names: > items: > - const: s_axi_aclk > - const: dac_clk > minItems: 1 > > '#io-backend-cells': > const: 0 > > required: > - compatible > - dmas > - reg > - clocks > > allOf: > - if: > properties: > compatible: > contains: > const: adi,axi-ad3552r > then: > $ref: /schemas/spi/spi-controller.yaml# > properties: > clocks: > minItems: 2 > clock-names: > minItems: 2 > else: > properties: > clocks: > maxItems: 1 > clock-names: > maxItems: 1 I guess in this case it could even be clock-names: false. One does not make much sense. - Nuno Sá
On 10/24/24 7:37 AM, Nuno Sá wrote: > On Thu, 2024-10-24 at 11:28 +0200, Angelo Dureghello wrote: >> Hi Conor, >> >> On 22.10.2024 18:22, Conor Dooley wrote: >>> On Mon, Oct 21, 2024 at 02:40:12PM +0200, Angelo Dureghello wrote: >>>> From: Angelo Dureghello <adureghello@baylibre.com> >>>> >>>> Add a new compatible and related bindigns for the fpga-based >>>> "ad3552r" AXI IP core, a variant of the generic AXI DAC IP. >>>> >>>> The AXI "ad3552r" IP is a very similar HDL (fpga) variant of the >>>> generic AXI "DAC" IP, intended to control ad3552r and similar chips, >>>> mainly to reach high speed transfer rates using a QSPI DDR >>>> (dobule-data-rate) interface. >>>> >>>> The ad3552r device is defined as a child of the AXI DAC, that in >>>> this case is acting as an SPI controller. >>>> >>>> Note, #io-backend is present because it is possible (in theory anyway) >>>> to use a separate controller for the control path than that used >>>> for the datapath. >>>> >>>> Signed-off-by: Angelo Dureghello <adureghello@baylibre.com> >>>> --- >>>> .../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 69 +++++++++++++++++++++- >>>> 1 file changed, 66 insertions(+), 3 deletions(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml >>>> b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml >>>> index a55e9bfc66d7..0aabb210f26d 100644 >>>> --- a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml >>>> +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml >>>> @@ -19,11 +19,13 @@ description: | >>>> memory via DMA into the DAC. >>>> >>>> https://wiki.analog.com/resources/fpga/docs/axi_dac_ip >>>> + https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html >>>> >>>> properties: >>>> compatible: >>>> enum: >>>> - adi,axi-dac-9.1.b >>>> + - adi,axi-ad3552r >>>> >>>> reg: >>>> maxItems: 1 >>>> @@ -36,7 +38,12 @@ properties: >>>> - const: tx >>>> >>>> clocks: >>>> - maxItems: 1 >>>> + minItems: 1 >>>> + maxItems: 2 >>>> + >>>> + clock-names: >>>> + minItems: 1 >>>> + maxItems: 2 >>>> >>>> '#io-backend-cells': >>>> const: 0 >>>> @@ -47,7 +54,31 @@ required: >>>> - reg >>>> - clocks >>>> >>>> -additionalProperties: false >>>> +allOf: >>>> + - if: >>>> + properties: >>>> + compatible: >>>> + contains: >>>> + const: adi,axi-ad3552r >>>> + then: >>>> + $ref: /schemas/spi/spi-controller.yaml# >>>> + properties: >>>> + clocks: >>>> + minItems: 2 >>>> + maxItems: 2 >>> >>> Is this maxItems required? It matches the outer maximum. >>> >>>> + clock-names: >>>> + items: >>>> + - const: s_axi_aclk >>>> + - const: dac_clk >>> >>> The names are the same in both cases, you can move the definitions >>> outside of the if/then/else stuff and only constrain it here. >>> >> thanks, could you maybe have a look if it's ok now ? >> (maxItems not needed for a const list) >> >> clocks: >> minItems: 1 >> maxItems: 2 >> >> clock-names: >> items: >> - const: s_axi_aclk >> - const: dac_clk >> minItems: 1 >> >> '#io-backend-cells': >> const: 0 >> >> required: >> - compatible >> - dmas >> - reg >> - clocks >> >> allOf: >> - if: >> properties: >> compatible: >> contains: >> const: adi,axi-ad3552r >> then: >> $ref: /schemas/spi/spi-controller.yaml# >> properties: >> clocks: >> minItems: 2 >> clock-names: >> minItems: 2 For this one, I think we also need: required: - clock-names >> else: >> properties: >> clocks: >> maxItems: 1 >> clock-names: >> maxItems: 1 > > I guess in this case it could even be clock-names: false. One does not make much > sense. > > - Nuno Sá > >
On Thu, Oct 24, 2024 at 09:43:02AM -0500, David Lechner wrote: > >>> > >> thanks, could you maybe have a look if it's ok now ? > >> (maxItems not needed for a const list) > >> > >> clocks: > >> minItems: 1 > >> maxItems: 2 > >> > >> clock-names: > >> items: > >> - const: s_axi_aclk > >> - const: dac_clk > >> minItems: 1 > >> > >> '#io-backend-cells': > >> const: 0 > >> > >> required: > >> - compatible > >> - dmas > >> - reg > >> - clocks > >> > >> allOf: > >> - if: > >> properties: > >> compatible: > >> contains: > >> const: adi,axi-ad3552r > >> then: > >> $ref: /schemas/spi/spi-controller.yaml# > >> properties: > >> clocks: > >> minItems: 2 > >> clock-names: > >> minItems: 2 > > > For this one, I think we also need: > > required: > - clock-names Ye, Angelo had that in the version posted in response to the driver patch. This looks ~correct. > > >> else: > >> properties: > >> clocks: > >> maxItems: 1 > >> clock-names: > >> maxItems: 1 > > > > I guess in this case it could even be clock-names: false. One does not make much > > sense. And since it is not mandatory, doubly useless.
diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml index a55e9bfc66d7..0aabb210f26d 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml @@ -19,11 +19,13 @@ description: | memory via DMA into the DAC. https://wiki.analog.com/resources/fpga/docs/axi_dac_ip + https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html properties: compatible: enum: - adi,axi-dac-9.1.b + - adi,axi-ad3552r reg: maxItems: 1 @@ -36,7 +38,12 @@ properties: - const: tx clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 '#io-backend-cells': const: 0 @@ -47,7 +54,31 @@ required: - reg - clocks -additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: adi,axi-ad3552r + then: + $ref: /schemas/spi/spi-controller.yaml# + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: s_axi_aclk + - const: dac_clk + else: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: s_axi_aclk + +unevaluatedProperties: false examples: - | @@ -57,6 +88,38 @@ examples: dmas = <&tx_dma 0>; dma-names = "tx"; #io-backend-cells = <0>; - clocks = <&axi_clk>; + clocks = <&clkc 15>; + clock-names = "s_axi_aclk"; + }; + + - | + #include <dt-bindings/gpio/gpio.h> + axi_dac: spi@44a70000 { + compatible = "adi,axi-ad3552r"; + reg = <0x44a70000 0x1000>; + dmas = <&dac_tx_dma 0>; + dma-names = "tx"; + #io-backend-cells = <0>; + clocks = <&clkc 15>, <&ref_clk>; + clock-names = "s_axi_aclk", "dac_clk"; + + #address-cells = <1>; + #size-cells = <0>; + + dac@0 { + compatible = "adi,ad3552r"; + reg = <0>; + reset-gpios = <&gpio0 92 GPIO_ACTIVE_HIGH>; + io-backends = <&axi_dac>; + spi-max-frequency = <20000000>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + adi,output-range-microvolt = <(-10000000) (10000000)>; + }; + }; }; ...