| Message ID | 20241023102108.5980-3-Dhananjay.Ugwekar@amd.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Delegated to: | Mario Limonciello |
| Headers | show |
| Series | cpufreq/amd-pstate:Cleanups | expand |
On Wed, Oct 23, 2024 at 10:21:08AM +0000, Dhananjay Ugwekar wrote: > MSR_AMD_CPPC_ENABLE is a write once register, i.e. attempting to clear > it is futile, it will not take effect. Hence, return if disable (0) > argument is passed to the msr_cppc_enable() > > Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com> Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com> > --- > drivers/cpufreq/amd-pstate.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c > index 0b4a4d69c14d..576251e61ce0 100644 > --- a/drivers/cpufreq/amd-pstate.c > +++ b/drivers/cpufreq/amd-pstate.c > @@ -311,6 +311,12 @@ static inline int msr_cppc_enable(bool enable) > int ret, cpu; > unsigned long logical_proc_id_mask = 0; > > + /* > + * MSR_AMD_CPPC_ENABLE is write-once, once set it cannot be cleared. > + */ > + if (!enable) > + return 0; > + > if (enable == cppc_enabled) > return 0; > > -- > 2.34.1 >
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 0b4a4d69c14d..576251e61ce0 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -311,6 +311,12 @@ static inline int msr_cppc_enable(bool enable) int ret, cpu; unsigned long logical_proc_id_mask = 0; + /* + * MSR_AMD_CPPC_ENABLE is write-once, once set it cannot be cleared. + */ + if (!enable) + return 0; + if (enable == cppc_enabled) return 0;
MSR_AMD_CPPC_ENABLE is a write once register, i.e. attempting to clear it is futile, it will not take effect. Hence, return if disable (0) argument is passed to the msr_cppc_enable() Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com> --- drivers/cpufreq/amd-pstate.c | 6 ++++++ 1 file changed, 6 insertions(+)