| Message ID | 20241015081603.30643-5-quic_qqzhou@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for APPS SMMU on QCS615 | expand |
On 15.10.2024 10:16 AM, Qingqing Zhou wrote: > Add the APPS SMMU node for QCS615 platform. Add the dma-ranges > to limit DMA address range to 36bit width to align with system > architecture. > > Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs615.dtsi | 74 ++++++++++++++++++++++++++++ > 1 file changed, 74 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > index 027c5125f36b..fcba83fca7cf 100644 > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > @@ -379,6 +379,7 @@ > soc: soc@0 { > compatible = "simple-bus"; > ranges = <0 0 0 0 0x10 0>; > + dma-ranges = <0 0 0 0 0x10 0>; > #address-cells = <2>; > #size-cells = <2>; > > @@ -524,6 +525,79 @@ > reg = <0x0 0x0c3f0000 0x0 0x400>; > }; > > + apps_smmu: iommu@15000000 { > + compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > + reg = <0x0 0x15000000 0x0 0x80000>; > + #iommu-cells = <2>; > + #global-interrupts = <1>; > + > + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, The list seems perfectly sorted, which is suspicious.. if we set i = n - #global-interrupts, interrupt[i] signifies an error in the i-th context bank. If the order is wrong, we'll get bogus reports Also, this is not aligned properly ('<' under '<') Konrad
在 10/18/2024 4:05 AM, Konrad Dybcio 写道: > On 15.10.2024 10:16 AM, Qingqing Zhou wrote: >> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges >> to limit DMA address range to 36bit width to align with system >> architecture. >> >> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcs615.dtsi | 74 ++++++++++++++++++++++++++++ >> 1 file changed, 74 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> index 027c5125f36b..fcba83fca7cf 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> @@ -379,6 +379,7 @@ >> soc: soc@0 { >> compatible = "simple-bus"; >> ranges = <0 0 0 0 0x10 0>; >> + dma-ranges = <0 0 0 0 0x10 0>; >> #address-cells = <2>; >> #size-cells = <2>; >> >> @@ -524,6 +525,79 @@ >> reg = <0x0 0x0c3f0000 0x0 0x400>; >> }; >> >> + apps_smmu: iommu@15000000 { >> + compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500"; >> + reg = <0x0 0x15000000 0x0 0x80000>; >> + #iommu-cells = <2>; >> + #global-interrupts = <1>; >> + >> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, > > The list seems perfectly sorted, which is suspicious.. if we set > i = n - #global-interrupts, interrupt[i] signifies an error in the i-th > context bank. If the order is wrong, we'll get bogus reports Thanks for the review, the list refers to Qualcomm Interrupts design spec, checking this platform again, the list is right, first line is global interrupt and the others are context interrupts with right order. > > Also, this is not aligned properly ('<' under '<') Got it, will update and align the spaces in next version. > > Konrad
在 10/18/2024 2:20 PM, Qingqing Zhou 写道: > > > 在 10/18/2024 4:05 AM, Konrad Dybcio 写道: >> On 15.10.2024 10:16 AM, Qingqing Zhou wrote: >>> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges >>> to limit DMA address range to 36bit width to align with system >>> architecture. >>> >>> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 74 ++++++++++++++++++++++++++++ >>> 1 file changed, 74 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >>> index 027c5125f36b..fcba83fca7cf 100644 >>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >>> @@ -379,6 +379,7 @@ >>> soc: soc@0 { >>> compatible = "simple-bus"; >>> ranges = <0 0 0 0 0x10 0>; >>> + dma-ranges = <0 0 0 0 0x10 0>; >>> #address-cells = <2>; >>> #size-cells = <2>; >>> >>> @@ -524,6 +525,79 @@ >>> reg = <0x0 0x0c3f0000 0x0 0x400>; >>> }; >>> >>> + apps_smmu: iommu@15000000 { >>> + compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500"; >>> + reg = <0x0 0x15000000 0x0 0x80000>; >>> + #iommu-cells = <2>; >>> + #global-interrupts = <1>; >>> + >>> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, >> >> The list seems perfectly sorted, which is suspicious.. if we set >> i = n - #global-interrupts, interrupt[i] signifies an error in the i-th >> context bank. If the order is wrong, we'll get bogus reports > Thanks for the review, the list refers to Qualcomm Interrupts design spec, checking this platform again, the list is right, first line is global interrupt and the others are context interrupts with right order. Hi Konrad, Hope above comments explain your question. If no more questions from you, I will post the next version. Thanks. >> >> Also, this is not aligned properly ('<' under '<') > Got it, will update and align the spaces in next version. >> >> Konrad > >
On 23.10.2024 7:48 AM, Qingqing Zhou wrote: > > > 在 10/18/2024 2:20 PM, Qingqing Zhou 写道: >> >> >> 在 10/18/2024 4:05 AM, Konrad Dybcio 写道: >>> On 15.10.2024 10:16 AM, Qingqing Zhou wrote: >>>> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges >>>> to limit DMA address range to 36bit width to align with system >>>> architecture. >>>> >>>> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> >>>> --- >>>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 74 ++++++++++++++++++++++++++++ >>>> 1 file changed, 74 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >>>> index 027c5125f36b..fcba83fca7cf 100644 >>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >>>> @@ -379,6 +379,7 @@ >>>> soc: soc@0 { >>>> compatible = "simple-bus"; >>>> ranges = <0 0 0 0 0x10 0>; >>>> + dma-ranges = <0 0 0 0 0x10 0>; >>>> #address-cells = <2>; >>>> #size-cells = <2>; >>>> >>>> @@ -524,6 +525,79 @@ >>>> reg = <0x0 0x0c3f0000 0x0 0x400>; >>>> }; >>>> >>>> + apps_smmu: iommu@15000000 { >>>> + compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500"; >>>> + reg = <0x0 0x15000000 0x0 0x80000>; >>>> + #iommu-cells = <2>; >>>> + #global-interrupts = <1>; >>>> + >>>> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, >>> >>> The list seems perfectly sorted, which is suspicious.. if we set >>> i = n - #global-interrupts, interrupt[i] signifies an error in the i-th >>> context bank. If the order is wrong, we'll get bogus reports >> Thanks for the review, the list refers to Qualcomm Interrupts design spec, checking this platform again, the list is right, first line is global interrupt and the others are context interrupts with right order. > Hi Konrad, > Hope above comments explain your question. If no more questions from you, I will post the next version. Thanks. Sorry, forgot to reply. I was able to confirm this is just a happy coincidence with the numbers. Konrad
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index 027c5125f36b..fcba83fca7cf 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -379,6 +379,7 @@ soc: soc@0 { compatible = "simple-bus"; ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; #address-cells = <2>; #size-cells = <2>; @@ -524,6 +525,79 @@ reg = <0x0 0x0c3f0000 0x0 0x400>; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
Add the APPS SMMU node for QCS615 platform. Add the dma-ranges to limit DMA address range to 36bit width to align with system architecture. Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 74 ++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+)