| Message ID | 20241011074619.796580-2-quic_kriskura@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add Devicetree support for USB controllers on QCS8300 | expand |
On 11.10.2024 9:46 AM, Krishna Kurapati wrote: The commit title should include a `qcs8300: ` part, like others in the directory (see git log --oneline arch/arm64/boot/dts/qcom). > Add support for USB controllers on QCS8300. The second > controller is only High Speed capable. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 168 ++++++++++++++++++++++++++ > 1 file changed, 168 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > index 2c35f96c3f28..4e6ba9f49b95 100644 > --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > @@ -1363,6 +1363,174 @@ IPCC_MPROC_SIGNAL_GLINK_QMP > qcom,remote-pid = <5>; > }; > }; > + > + usb_1_hsphy: phy@8904000 { > + compatible = "qcom,qcs8300-usb-hs-phy", > + "qcom,usb-snps-hs-7nm-phy"; > + reg = <0x0 0x8904000 0x0 0x400>; Please pad the address parts to 8 hex digits with leading zeroes. > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; > + > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + usb_2_hsphy: phy@8906000 { > + compatible = "qcom,qcs8300-usb-hs-phy", > + "qcom,usb-snps-hs-7nm-phy"; > + reg = <0x0 0x08906000 0x0 0x400>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_USB2_PHY_SEC_BCR>; > + > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + usb_qmpphy: phy@8907000 { > + compatible = "qcom,qcs8300-qmp-usb3-uni-phy"; > + reg = <0x0 0x8907000 0x0 0x2000>; > + > + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > + <&gcc GCC_USB_CLKREF_EN>, > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "aux", "ref", "com_aux", "pipe"; Please make this a vertical list like in the node below. [...] > + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, QCOM_ICC_TAG_ALWAYS, see x1e80100.dtsi > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; > + interconnect-names = "usb-ddr", "apps-usb"; > + > + wakeup-source; > + > + status = "disabled"; > + > + usb_1_dwc3: usb@a600000 { > + compatible = "snps,dwc3"; > + reg = <0x0 0x0a600000 0x0 0xe000>; > + interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; > + iommus = <&apps_smmu 0x80 0x0>; > + phys = <&usb_1_hsphy>, <&usb_qmpphy>; > + phy-names = "usb2-phy", "usb3-phy"; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; That's a very low number of quirks.. Should we have some more? Should it also be marked dma-coherent? Identical comments for the second instance. Konrad
On 10/25/2024 11:58 PM, Konrad Dybcio wrote: > On 11.10.2024 9:46 AM, Krishna Kurapati wrote: > > The commit title should include a `qcs8300: ` part, like others in > the directory (see git log --oneline arch/arm64/boot/dts/qcom). > >> Add support for USB controllers on QCS8300. The second >> controller is only High Speed capable. >> >> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 168 ++++++++++++++++++++++++++ >> 1 file changed, 168 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> index 2c35f96c3f28..4e6ba9f49b95 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> @@ -1363,6 +1363,174 @@ IPCC_MPROC_SIGNAL_GLINK_QMP >> qcom,remote-pid = <5>; >> }; >> }; >> + >> + usb_1_hsphy: phy@8904000 { >> + compatible = "qcom,qcs8300-usb-hs-phy", >> + "qcom,usb-snps-hs-7nm-phy"; >> + reg = <0x0 0x8904000 0x0 0x400>; > > Please pad the address parts to 8 hex digits with leading zeroes. > >> + >> + clocks = <&rpmhcc RPMH_CXO_CLK>; >> + clock-names = "ref"; >> + >> + resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; >> + >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + usb_2_hsphy: phy@8906000 { >> + compatible = "qcom,qcs8300-usb-hs-phy", >> + "qcom,usb-snps-hs-7nm-phy"; >> + reg = <0x0 0x08906000 0x0 0x400>; >> + >> + clocks = <&rpmhcc RPMH_CXO_CLK>; >> + clock-names = "ref"; >> + >> + resets = <&gcc GCC_USB2_PHY_SEC_BCR>; >> + >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + usb_qmpphy: phy@8907000 { >> + compatible = "qcom,qcs8300-qmp-usb3-uni-phy"; >> + reg = <0x0 0x8907000 0x0 0x2000>; >> + >> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, >> + <&gcc GCC_USB_CLKREF_EN>, >> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, >> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; >> + clock-names = "aux", "ref", "com_aux", "pipe"; > > Please make this a vertical list like in the node below. > > [...] > >> + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, > > QCOM_ICC_TAG_ALWAYS, see x1e80100.dtsi > >> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; >> + interconnect-names = "usb-ddr", "apps-usb"; >> + >> + wakeup-source; >> + >> + status = "disabled"; >> + >> + usb_1_dwc3: usb@a600000 { >> + compatible = "snps,dwc3"; >> + reg = <0x0 0x0a600000 0x0 0xe000>; >> + interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; >> + iommus = <&apps_smmu 0x80 0x0>; >> + phys = <&usb_1_hsphy>, <&usb_qmpphy>; >> + phy-names = "usb2-phy", "usb3-phy"; >> + snps,dis_u2_susphy_quirk; >> + snps,dis_enblslpm_quirk; > > That's a very low number of quirks.. Should we have some more? > snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; snps,ssp-u3-u0-quirk; I would actually like to add these as well, but there is no precedent in upstream as to what quirks to add for usb nodes, so I kept only a couple of them. Ideally downstream we disable u1u2 for almost all targets because of some issues in the past. (atleast during tethering use cases, but I need to double check though). > Should it also be marked dma-coherent? > ACK. Regards, Krishna,
On 26.10.2024 6:56 PM, Krishna Kurapati wrote: > > > On 10/25/2024 11:58 PM, Konrad Dybcio wrote: >> On 11.10.2024 9:46 AM, Krishna Kurapati wrote: >> >> The commit title should include a `qcs8300: ` part, like others in >> the directory (see git log --oneline arch/arm64/boot/dts/qcom). >> >>> Add support for USB controllers on QCS8300. The second >>> controller is only High Speed capable. >>> >>> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 168 ++++++++++++++++++++++++++ >>> 1 file changed, 168 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >>> index 2c35f96c3f28..4e6ba9f49b95 100644 >>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >>> @@ -1363,6 +1363,174 @@ IPCC_MPROC_SIGNAL_GLINK_QMP >>> qcom,remote-pid = <5>; >>> }; >>> }; >>> + >>> + usb_1_hsphy: phy@8904000 { >>> + compatible = "qcom,qcs8300-usb-hs-phy", >>> + "qcom,usb-snps-hs-7nm-phy"; >>> + reg = <0x0 0x8904000 0x0 0x400>; >> >> Please pad the address parts to 8 hex digits with leading zeroes. >> >>> + >>> + clocks = <&rpmhcc RPMH_CXO_CLK>; >>> + clock-names = "ref"; >>> + >>> + resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; >>> + >>> + #phy-cells = <0>; >>> + >>> + status = "disabled"; >>> + }; >>> + >>> + usb_2_hsphy: phy@8906000 { >>> + compatible = "qcom,qcs8300-usb-hs-phy", >>> + "qcom,usb-snps-hs-7nm-phy"; >>> + reg = <0x0 0x08906000 0x0 0x400>; >>> + >>> + clocks = <&rpmhcc RPMH_CXO_CLK>; >>> + clock-names = "ref"; >>> + >>> + resets = <&gcc GCC_USB2_PHY_SEC_BCR>; >>> + >>> + #phy-cells = <0>; >>> + >>> + status = "disabled"; >>> + }; >>> + >>> + usb_qmpphy: phy@8907000 { >>> + compatible = "qcom,qcs8300-qmp-usb3-uni-phy"; >>> + reg = <0x0 0x8907000 0x0 0x2000>; >>> + >>> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, >>> + <&gcc GCC_USB_CLKREF_EN>, >>> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, >>> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; >>> + clock-names = "aux", "ref", "com_aux", "pipe"; >> >> Please make this a vertical list like in the node below. >> >> [...] >> >>> + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, >> >> QCOM_ICC_TAG_ALWAYS, see x1e80100.dtsi >> >>> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; >>> + interconnect-names = "usb-ddr", "apps-usb"; >>> + >>> + wakeup-source; >>> + >>> + status = "disabled"; >>> + >>> + usb_1_dwc3: usb@a600000 { >>> + compatible = "snps,dwc3"; >>> + reg = <0x0 0x0a600000 0x0 0xe000>; >>> + interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; >>> + iommus = <&apps_smmu 0x80 0x0>; >>> + phys = <&usb_1_hsphy>, <&usb_qmpphy>; >>> + phy-names = "usb2-phy", "usb3-phy"; >>> + snps,dis_u2_susphy_quirk; >>> + snps,dis_enblslpm_quirk; >> >> That's a very low number of quirks.. Should we have some more? >> > > snps,dis-u1-entry-quirk; > snps,dis-u2-entry-quirk; > snps,dis_u2_susphy_quirk; > snps,ssp-u3-u0-quirk; > > I would actually like to add these as well, but there is no precedent in upstream as to what quirks to add for usb nodes Every single one that applies to the hardware ;) > , so I kept only a couple of them. Ideally downstream we disable u1u2 for almost all targets because of some issues in the past. (atleast during tethering use cases, but I need to double check though). Does 5b8baed4b881 ("arm64: dts: qcom: sc7180: Disable SuperSpeed instances in park mode") apply here too? Konrad
On 10/28/2024 5:08 PM, Konrad Dybcio wrote: > On 26.10.2024 6:56 PM, Krishna Kurapati wrote: >> >> >> On 10/25/2024 11:58 PM, Konrad Dybcio wrote: >>> On 11.10.2024 9:46 AM, Krishna Kurapati wrote: >>> >>> The commit title should include a `qcs8300: ` part, like others in >>> the directory (see git log --oneline arch/arm64/boot/dts/qcom). >>> >>>> Add support for USB controllers on QCS8300. The second >>>> controller is only High Speed capable. >>>> >>>> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> >>>> --- >>>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 168 ++++++++++++++++++++++++++ >>>> 1 file changed, 168 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >>>> index 2c35f96c3f28..4e6ba9f49b95 100644 >>>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >>>> @@ -1363,6 +1363,174 @@ IPCC_MPROC_SIGNAL_GLINK_QMP >>>> qcom,remote-pid = <5>; >>>> }; >>>> }; >>>> + >>>> + usb_1_hsphy: phy@8904000 { >>>> + compatible = "qcom,qcs8300-usb-hs-phy", >>>> + "qcom,usb-snps-hs-7nm-phy"; >>>> + reg = <0x0 0x8904000 0x0 0x400>; >>> >>> Please pad the address parts to 8 hex digits with leading zeroes. >>> >>>> + >>>> + clocks = <&rpmhcc RPMH_CXO_CLK>; >>>> + clock-names = "ref"; >>>> + >>>> + resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; >>>> + >>>> + #phy-cells = <0>; >>>> + >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + usb_2_hsphy: phy@8906000 { >>>> + compatible = "qcom,qcs8300-usb-hs-phy", >>>> + "qcom,usb-snps-hs-7nm-phy"; >>>> + reg = <0x0 0x08906000 0x0 0x400>; >>>> + >>>> + clocks = <&rpmhcc RPMH_CXO_CLK>; >>>> + clock-names = "ref"; >>>> + >>>> + resets = <&gcc GCC_USB2_PHY_SEC_BCR>; >>>> + >>>> + #phy-cells = <0>; >>>> + >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + usb_qmpphy: phy@8907000 { >>>> + compatible = "qcom,qcs8300-qmp-usb3-uni-phy"; >>>> + reg = <0x0 0x8907000 0x0 0x2000>; >>>> + >>>> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, >>>> + <&gcc GCC_USB_CLKREF_EN>, >>>> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, >>>> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; >>>> + clock-names = "aux", "ref", "com_aux", "pipe"; >>> >>> Please make this a vertical list like in the node below. >>> >>> [...] >>> >>>> + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, >>> >>> QCOM_ICC_TAG_ALWAYS, see x1e80100.dtsi >>> >>>> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; >>>> + interconnect-names = "usb-ddr", "apps-usb"; >>>> + >>>> + wakeup-source; >>>> + >>>> + status = "disabled"; >>>> + >>>> + usb_1_dwc3: usb@a600000 { >>>> + compatible = "snps,dwc3"; >>>> + reg = <0x0 0x0a600000 0x0 0xe000>; >>>> + interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; >>>> + iommus = <&apps_smmu 0x80 0x0>; >>>> + phys = <&usb_1_hsphy>, <&usb_qmpphy>; >>>> + phy-names = "usb2-phy", "usb3-phy"; >>>> + snps,dis_u2_susphy_quirk; >>>> + snps,dis_enblslpm_quirk; >>> >>> That's a very low number of quirks.. Should we have some more? >>> >> >> snps,dis-u1-entry-quirk; >> snps,dis-u2-entry-quirk; >> snps,dis_u2_susphy_quirk; >> snps,ssp-u3-u0-quirk; >> >> I would actually like to add these as well, but there is no precedent in upstream as to what quirks to add for usb nodes > > Every single one that applies to the hardware ;) > >> , so I kept only a couple of them. Ideally downstream we disable u1u2 for almost all targets because of some issues in the past. (atleast during tethering use cases, but I need to double check though). > > Does > > 5b8baed4b881 ("arm64: dts: qcom: sc7180: Disable SuperSpeed instances in park mode") > > apply here too? > QCS8300 is Gen-2, so that quirk is not needed. Regards, Krishna,
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 2c35f96c3f28..4e6ba9f49b95 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -1363,6 +1363,174 @@ IPCC_MPROC_SIGNAL_GLINK_QMP qcom,remote-pid = <5>; }; }; + + usb_1_hsphy: phy@8904000 { + compatible = "qcom,qcs8300-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0x0 0x8904000 0x0 0x400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_2_hsphy: phy@8906000 { + compatible = "qcom,qcs8300-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0x0 0x08906000 0x0 0x400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_USB2_PHY_SEC_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_qmpphy: phy@8907000 { + compatible = "qcom,qcs8300-qmp-usb3-uni-phy"; + reg = <0x0 0x8907000 0x0 0x2000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; + reset-names = "phy", "phy_phy"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + + #clock-cells = <0>; + clock-output-names = "usb3_prim_phy_pipe_clk_src"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,qcs8300-dwc3", "qcom,dwc3"; + reg = <0x0 0x0a6f8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + wakeup-source; + + status = "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0x0 0x0a600000 0x0 0xe000>; + interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x80 0x0>; + phys = <&usb_1_hsphy>, <&usb_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + }; + }; + + usb_2: usb@a4f8800 { + compatible = "qcom,qcs8300-dwc3", "qcom,dwc3"; + reg = <0x0 0x0a4f8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <120000000>; + + interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_BOTH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; + + power-domains = <&gcc GCC_USB20_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB20_PRIM_BCR>; + + interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + qcom,select-utmi-as-pipe-clk; + wakeup-source; + + status = "disabled"; + + usb_2_dwc3: usb@a400000 { + compatible = "snps,dwc3"; + reg = <0x0 0x0a400000 0x0 0xe000>; + interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x20 0x0>; + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + }; + }; }; arch_timer: timer {
Add support for USB controllers on QCS8300. The second controller is only High Speed capable. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 168 ++++++++++++++++++++++++++ 1 file changed, 168 insertions(+)