diff mbox series

[v3,1/2] scsi: ufs: core: check asymmetric connected lanes

Message ID e82b4b65b5f6501a687c624dd06e5c362e160f32.1728544727.git.hy50.seo@samsung.com (mailing list archive)
State Accepted
Headers show
Series processing of asymmetric connected lanes | expand

Commit Message

SEO HOYOUNG Oct. 10, 2024, 7:52 a.m. UTC
Performance problems may occur if there is a problem with the
asymmetric connected lane such as h/w failure.
Currently, only check connected lane for rx/tx is checked if it is not 0.
But it should also be checked if it is asymmetrically connected.

Signed-off-by: SEO HOYOUNG <hy50.seo@samsung.com>
---
 drivers/ufs/core/ufshcd.c | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Bart Van Assche Oct. 15, 2024, 6:16 p.m. UTC | #1
On 10/10/24 12:52 AM, SEO HOYOUNG wrote:
> Performance problems may occur if there is a problem with the
> asymmetric connected lane such as h/w failure.
> Currently, only check connected lane for rx/tx is checked if it is not 0.
> But it should also be checked if it is asymmetrically connected.
> 
> Signed-off-by: SEO HOYOUNG <hy50.seo@samsung.com>
> ---
>   drivers/ufs/core/ufshcd.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
> index 24a32e2fd75e..387eec6f19ef 100644
> --- a/drivers/ufs/core/ufshcd.c
> +++ b/drivers/ufs/core/ufshcd.c
> @@ -4540,6 +4540,14 @@ static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
>   		return -EINVAL;
>   	}
>   
> +	if (pwr_info->lane_rx != pwr_info->lane_tx) {
> +		dev_err(hba->dev, "%s: asymmetric connected lanes. rx=%d, tx=%d\n",
> +			__func__,
> +				pwr_info->lane_rx,
> +				pwr_info->lane_tx);
> +		return -EINVAL;
> +	}
> +
>   	/*
>   	 * First, get the maximum gears of HS speed.
>   	 * If a zero value, it means there is no HSGEAR capability.

It seems to me that symmetry of the number of lanes is required by the
UFS standard? From the UFS standard: "An equal number of downstream and
upstream lanes shall be provided in each link." Hence:

Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Martin K. Petersen Oct. 25, 2024, 6:37 p.m. UTC | #2
> Performance problems may occur if there is a problem with the
> asymmetric connected lane such as h/w failure. Currently, only check
> connected lane for rx/tx is checked if it is not 0. But it should also
> be checked if it is asymmetrically connected.

Applied to 6.13/scsi-staging, thanks!
diff mbox series

Patch

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 24a32e2fd75e..387eec6f19ef 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -4540,6 +4540,14 @@  static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
 		return -EINVAL;
 	}
 
+	if (pwr_info->lane_rx != pwr_info->lane_tx) {
+		dev_err(hba->dev, "%s: asymmetric connected lanes. rx=%d, tx=%d\n",
+			__func__,
+				pwr_info->lane_rx,
+				pwr_info->lane_tx);
+		return -EINVAL;
+	}
+
 	/*
 	 * First, get the maximum gears of HS speed.
 	 * If a zero value, it means there is no HSGEAR capability.