| Message ID | 20241011103346.22925-1-quic_vdadhani@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v1] arm64: dts: qcom: qcs615: Add QUPv3 configuration | expand |
On 11.10.2024 12:33 PM, Viken Dadhaniya wrote: > Add DT support for QUPv3 Serial Engines. > > Co-developed-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> > Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> > Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> > --- [...] > + qup_opp_table: opp-table-qup { > + compatible = "operating-points-v2"; opp-shared; > + > + opp-75000000 { > + opp-hz = /bits/ 64 <75000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-128000000 { > + opp-hz = /bits/ 64 <128000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + > psci { > compatible = "arm,psci-1.0"; > method = "smc"; > @@ -392,6 +427,24 @@ > #size-cells = <1>; > }; > > + gpi_dma0: qcom,gpi-dma@800000 { > + compatible = "qcom,sdm845-gpi-dma"; You must define a new compatible for qcs615, sdm845 is used as a fallback (so that we don't have to add new driver entries). You will however need to submit a separate dt-bindings change. > + reg = <0x0 0x800000 0x0 0x60000>; > + #dma-cells = <3>; > + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; > + dma-channels = <8>; > + dma-channel-mask = <0xf>; > + iommus = <&apps_smmu 0xd6 0x0>; > + status = "disabled"; Any reason? > + }; > + > qupv3_id_0: geniqup@8c0000 { > compatible = "qcom,geni-se-qup"; > reg = <0x0 0x8c0000 0x0 0x6000>; > @@ -400,6 +453,7 @@ > <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > clock-names = "m-ahb", > "s-ahb"; > + iommus = <&apps_smmu 0xc3 0x0>; This looks like a separate fix > #address-cells = <2>; > #size-cells = <2>; > status = "disabled"; > @@ -412,13 +466,377 @@ > pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>; > pinctrl-names = "default"; > interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; > - interconnects = <&aggre1_noc MASTER_QUP_0 0 > - &mc_virt SLAVE_EBI1 0>, > - <&gem_noc MASTER_APPSS_PROC 0 > - &config_noc SLAVE_QUP_0 0>; > + interconnects = <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; Why? Also, please use QCOM_ICC_TAG_ALWAYS instead of zeroes Konrad
On 10/26/2024 1:10 AM, Konrad Dybcio wrote: > On 11.10.2024 12:33 PM, Viken Dadhaniya wrote: >> Add DT support for QUPv3 Serial Engines. >> >> Co-developed-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> >> Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> >> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> >> --- > > [...] > >> + qup_opp_table: opp-table-qup { >> + compatible = "operating-points-v2"; > > opp-shared; Added in v2. > >> + >> + opp-75000000 { >> + opp-hz = /bits/ 64 <75000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-100000000 { >> + opp-hz = /bits/ 64 <100000000>; >> + required-opps = <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-128000000 { >> + opp-hz = /bits/ 64 <128000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> + >> psci { >> compatible = "arm,psci-1.0"; >> method = "smc"; >> @@ -392,6 +427,24 @@ >> #size-cells = <1>; >> }; >> >> + gpi_dma0: qcom,gpi-dma@800000 { >> + compatible = "qcom,sdm845-gpi-dma"; > > You must define a new compatible for qcs615, sdm845 is used as a fallback > (so that we don't have to add new driver entries). You will however need > to submit a separate dt-bindings change. We have added sdm845 in compatible due to below comment in driver file File: https://github.com/torvalds/linux/blob/81983758430957d9a5cb3333fe324fd70cf63e7e/drivers/dma/qcom/gpi.c#L2284 /* * Do not grow the list for compatible devices. Instead use * qcom,sdm845-gpi-dma (for ee_offset = 0x0) or qcom,sm6350-gpi-dma * (for ee_offset = 0x10000). */ Do we still require new compatible for qcs615 ? > >> + reg = <0x0 0x800000 0x0 0x60000>; >> + #dma-cells = <3>; >> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; >> + dma-channels = <8>; >> + dma-channel-mask = <0xf>; >> + iommus = <&apps_smmu 0xd6 0x0>; >> + status = "disabled"; > > Any reason? By default, we are disabling all nodes. In the target-specific file, we will update them based on the required use case. > >> + }; >> + >> qupv3_id_0: geniqup@8c0000 { >> compatible = "qcom,geni-se-qup"; >> reg = <0x0 0x8c0000 0x0 0x6000>; >> @@ -400,6 +453,7 @@ >> <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; >> clock-names = "m-ahb", >> "s-ahb"; >> + iommus = <&apps_smmu 0xc3 0x0>; > > This looks like a separate fix One QUP and UART (console) related change has been added as part of the base DTSI. Now, we are adding all remaining QUP and I2C/SPI/UART configurations with IOMMUs and other properties. Is there any specific reason to make this a separate fix? > >> #address-cells = <2>; >> #size-cells = <2>; >> status = "disabled"; >> @@ -412,13 +466,377 @@ >> pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>; >> pinctrl-names = "default"; >> interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; >> - interconnects = <&aggre1_noc MASTER_QUP_0 0 >> - &mc_virt SLAVE_EBI1 0>, >> - <&gem_noc MASTER_APPSS_PROC 0 >> - &config_noc SLAVE_QUP_0 0>; >> + interconnects = <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; > > Why? > > Also, please use QCOM_ICC_TAG_ALWAYS instead of zeroes Updated in v2. > > Konrad
On 11/10/2024 12:33, Viken Dadhaniya wrote: > Add DT support for QUPv3 Serial Engines. > > Co-developed-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> > Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> > Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> > --- > > Build Dependencies: > > Base: > https://lore.kernel.org/linux-devicetree/20240926-add_initial_support_for_qcs615-v3-5-e37617e91c62@quicinc.com/ > https://lore.kernel.org/linux-devicetree/20240926-add_initial_support_for_qcs615-v3-6-e37617e91c62@quicinc.com/ > > Clock: https://lore.kernel.org/linux-devicetree/20240920-qcs615-clock-driver-v2-3-2f6de44eb2aa@quicinc.com/ > ICC: https://lore.kernel.org/linux-devicetree/20240924143958.25-2-quic_rlaggysh@quicinc.com/ > Apps SMMU: https://lore.kernel.org/all/20241011063112.19087-1-quic_qqzhou@quicinc.com/ > --- > arch/arm64/boot/dts/qcom/qcs615.dtsi | 602 ++++++++++++++++++++++++++- > 1 file changed, 598 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > index 865ead601f85..9d7fc6fc5c6e 100644 > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > @@ -5,6 +5,7 @@ > > #include <dt-bindings/clock/qcom,qcs615-gcc.h> > #include <dt-bindings/clock/qcom,rpmh.h> > +#include <dt-bindings/dma/qcom-gpi.h> > #include <dt-bindings/interconnect/qcom,icc.h> > #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > @@ -17,6 +18,21 @@ > #address-cells = <2>; > #size-cells = <2>; > > + aliases { > + i2c1 = &i2c1; > + i2c2 = &i2c2; > + i2c3 = &i2c3; > + i2c4 = &i2c4; > + i2c5 = &i2c5; > + i2c6 = &i2c6; > + i2c7 = &i2c7; > + spi2 = &spi2; > + spi4 = &spi4; > + spi6 = &spi6; > + spi7 = &spi7; > + serial0 = &uart0; Bus aliases are not supposed to be specific to SoC. Drop them from SoC DTSI. > + }; > + > cpus { > #address-cells = <2>; > #size-cells = <0>; > @@ -296,6 +312,25 @@ > qcom,bcm-voters = <&apps_bcm_voter>; > }; > > + qup_opp_table: opp-table-qup { > + compatible = "operating-points-v2"; > + > + opp-75000000 { > + opp-hz = /bits/ 64 <75000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-128000000 { > + opp-hz = /bits/ 64 <128000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + > psci { > compatible = "arm,psci-1.0"; > method = "smc"; > @@ -392,6 +427,24 @@ > #size-cells = <1>; > }; > > + gpi_dma0: qcom,gpi-dma@800000 { That's again downstream code. Do not send us stuff from downstream. Best regards, Krzysztof
On Mon, Oct 28, 2024 at 04:49:43PM +0530, Viken Dadhaniya wrote: > > > On 10/26/2024 1:10 AM, Konrad Dybcio wrote: > > On 11.10.2024 12:33 PM, Viken Dadhaniya wrote: > > > Add DT support for QUPv3 Serial Engines. > > > > > > Co-developed-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> > > > Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> > > > Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> > > > --- > > > > [...] > > > > > @@ -392,6 +427,24 @@ > > > #size-cells = <1>; > > > }; > > > + gpi_dma0: qcom,gpi-dma@800000 { > > > + compatible = "qcom,sdm845-gpi-dma"; > > > > You must define a new compatible for qcs615, sdm845 is used as a fallback > > (so that we don't have to add new driver entries). You will however need > > to submit a separate dt-bindings change. > > We have added sdm845 in compatible due to below comment in driver file > > File: https://github.com/torvalds/linux/blob/81983758430957d9a5cb3333fe324fd70cf63e7e/drivers/dma/qcom/gpi.c#L2284 > > /* > * Do not grow the list for compatible devices. Instead use > * qcom,sdm845-gpi-dma (for ee_offset = 0x0) or qcom,sm6350-gpi-dma > * (for ee_offset = 0x10000). > */ > > Do we still require new compatible for qcs615 ? You are not living in the void space. `git grep qcom,sdm845-gpi-dma` immediately shows what is being expected. Please don't ignore existing work. > > >
On 28.10.2024 12:19 PM, Viken Dadhaniya wrote: > > > On 10/26/2024 1:10 AM, Konrad Dybcio wrote: >> On 11.10.2024 12:33 PM, Viken Dadhaniya wrote: >>> Add DT support for QUPv3 Serial Engines. >>> >>> Co-developed-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> >>> Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> >>> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> >>> --- >> >> [...] >> >>> + qup_opp_table: opp-table-qup { >>> + compatible = "operating-points-v2"; >> >> opp-shared; > > Added in v2. > >> >>> + >>> + opp-75000000 { >>> + opp-hz = /bits/ 64 <75000000>; >>> + required-opps = <&rpmhpd_opp_low_svs>; >>> + }; >>> + >>> + opp-100000000 { >>> + opp-hz = /bits/ 64 <100000000>; >>> + required-opps = <&rpmhpd_opp_svs>; >>> + }; >>> + >>> + opp-128000000 { >>> + opp-hz = /bits/ 64 <128000000>; >>> + required-opps = <&rpmhpd_opp_nom>; >>> + }; >>> + }; >>> + >>> psci { >>> compatible = "arm,psci-1.0"; >>> method = "smc"; >>> @@ -392,6 +427,24 @@ >>> #size-cells = <1>; >>> }; >>> + gpi_dma0: qcom,gpi-dma@800000 { >>> + compatible = "qcom,sdm845-gpi-dma"; >> >> You must define a new compatible for qcs615, sdm845 is used as a fallback >> (so that we don't have to add new driver entries). You will however need >> to submit a separate dt-bindings change. > > We have added sdm845 in compatible due to below comment in driver file > > File: https://github.com/torvalds/linux/blob/81983758430957d9a5cb3333fe324fd70cf63e7e/drivers/dma/qcom/gpi.c#L2284 > > /* > * Do not grow the list for compatible devices. Instead use > * qcom,sdm845-gpi-dma (for ee_offset = 0x0) or qcom,sm6350-gpi-dma > * (for ee_offset = 0x10000). > */ > > Do we still require new compatible for qcs615 ? The comment concerns the driver side. All devicetree compatible strings present in the tree must be documented in Documentation/devicetree/bindings/ which is where you should add your one as well. > >> >>> + reg = <0x0 0x800000 0x0 0x60000>; >>> + #dma-cells = <3>; >>> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; >>> + dma-channels = <8>; >>> + dma-channel-mask = <0xf>; >>> + iommus = <&apps_smmu 0xd6 0x0>; >>> + status = "disabled"; >> >> Any reason? > > By default, we are disabling all nodes. In the target-specific file, we will update them based on the required use case. > >> >>> + }; >>> + >>> qupv3_id_0: geniqup@8c0000 { >>> compatible = "qcom,geni-se-qup"; >>> reg = <0x0 0x8c0000 0x0 0x6000>; >>> @@ -400,6 +453,7 @@ >>> <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; >>> clock-names = "m-ahb", >>> "s-ahb"; >>> + iommus = <&apps_smmu 0xc3 0x0>; >> >> This looks like a separate fix > > One QUP and UART (console) related change has been added as part of the base DTSI. Now, we are adding all remaining QUP and I2C/SPI/UART configurations with IOMMUs and other properties. > > Is there any specific reason to make this a separate fix? Did this work properly before? Konrad
On 10/28/2024 5:58 PM, Dmitry Baryshkov wrote: > On Mon, Oct 28, 2024 at 04:49:43PM +0530, Viken Dadhaniya wrote: >> >> >> On 10/26/2024 1:10 AM, Konrad Dybcio wrote: >>> On 11.10.2024 12:33 PM, Viken Dadhaniya wrote: >>>> Add DT support for QUPv3 Serial Engines. >>>> >>>> Co-developed-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> >>>> Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> >>>> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> >>>> --- >>> >>> [...] >>> >>>> @@ -392,6 +427,24 @@ >>>> #size-cells = <1>; >>>> }; >>>> + gpi_dma0: qcom,gpi-dma@800000 { >>>> + compatible = "qcom,sdm845-gpi-dma"; >>> >>> You must define a new compatible for qcs615, sdm845 is used as a fallback >>> (so that we don't have to add new driver entries). You will however need >>> to submit a separate dt-bindings change. >> >> We have added sdm845 in compatible due to below comment in driver file >> >> File: https://github.com/torvalds/linux/blob/81983758430957d9a5cb3333fe324fd70cf63e7e/drivers/dma/qcom/gpi.c#L2284 >> >> /* >> * Do not grow the list for compatible devices. Instead use >> * qcom,sdm845-gpi-dma (for ee_offset = 0x0) or qcom,sm6350-gpi-dma >> * (for ee_offset = 0x10000). >> */ >> >> Do we still require new compatible for qcs615 ? > > You are not living in the void space. `git grep qcom,sdm845-gpi-dma` > immediately shows what is being expected. Please don't ignore existing > work. Thanks, Pushed separate patch for GPI documentation patch. https://lore.kernel.org/all/w66ki7lwrqol24iptikn7ccna25ujqoywjena5ulekf6vynxny@dylbj2r34h7l/T/ > >> >>> >
On 10/28/2024 5:03 PM, Krzysztof Kozlowski wrote: > On 11/10/2024 12:33, Viken Dadhaniya wrote: >> Add DT support for QUPv3 Serial Engines. >> >> Co-developed-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> >> Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> >> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> >> --- >> >> Build Dependencies: >> >> Base: >> https://lore.kernel.org/linux-devicetree/20240926-add_initial_support_for_qcs615-v3-5-e37617e91c62@quicinc.com/ >> https://lore.kernel.org/linux-devicetree/20240926-add_initial_support_for_qcs615-v3-6-e37617e91c62@quicinc.com/ >> >> Clock: https://lore.kernel.org/linux-devicetree/20240920-qcs615-clock-driver-v2-3-2f6de44eb2aa@quicinc.com/ >> ICC: https://lore.kernel.org/linux-devicetree/20240924143958.25-2-quic_rlaggysh@quicinc.com/ >> Apps SMMU: https://lore.kernel.org/all/20241011063112.19087-1-quic_qqzhou@quicinc.com/ >> --- >> arch/arm64/boot/dts/qcom/qcs615.dtsi | 602 ++++++++++++++++++++++++++- >> 1 file changed, 598 insertions(+), 4 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> index 865ead601f85..9d7fc6fc5c6e 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> @@ -5,6 +5,7 @@ >> >> #include <dt-bindings/clock/qcom,qcs615-gcc.h> >> #include <dt-bindings/clock/qcom,rpmh.h> >> +#include <dt-bindings/dma/qcom-gpi.h> >> #include <dt-bindings/interconnect/qcom,icc.h> >> #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> @@ -17,6 +18,21 @@ >> #address-cells = <2>; >> #size-cells = <2>; >> >> + aliases { >> + i2c1 = &i2c1; >> + i2c2 = &i2c2; >> + i2c3 = &i2c3; >> + i2c4 = &i2c4; >> + i2c5 = &i2c5; >> + i2c6 = &i2c6; >> + i2c7 = &i2c7; >> + spi2 = &spi2; >> + spi4 = &spi4; >> + spi6 = &spi6; >> + spi7 = &spi7; >> + serial0 = &uart0; > > Bus aliases are not supposed to be specific to SoC. Drop them from SoC DTSI. Sure, Updated in v3. > >> + }; >> + >> cpus { >> #address-cells = <2>; >> #size-cells = <0>; >> @@ -296,6 +312,25 @@ >> qcom,bcm-voters = <&apps_bcm_voter>; >> }; >> >> + qup_opp_table: opp-table-qup { >> + compatible = "operating-points-v2"; >> + >> + opp-75000000 { >> + opp-hz = /bits/ 64 <75000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-100000000 { >> + opp-hz = /bits/ 64 <100000000>; >> + required-opps = <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-128000000 { >> + opp-hz = /bits/ 64 <128000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> + >> psci { >> compatible = "arm,psci-1.0"; >> method = "smc"; >> @@ -392,6 +427,24 @@ >> #size-cells = <1>; >> }; >> >> + gpi_dma0: qcom,gpi-dma@800000 { > > That's again downstream code. Do not send us stuff from downstream. > Sure. updated in v3. > > > > Best regards, > Krzysztof >
On 10/28/2024 6:38 PM, Konrad Dybcio wrote: > On 28.10.2024 12:19 PM, Viken Dadhaniya wrote: >> >> >> On 10/26/2024 1:10 AM, Konrad Dybcio wrote: >>> On 11.10.2024 12:33 PM, Viken Dadhaniya wrote: >>>> Add DT support for QUPv3 Serial Engines. >>>> >>>> Co-developed-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> >>>> Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> >>>> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> >>>> --- >>> >>> [...] >>> >>>> + qup_opp_table: opp-table-qup { >>>> + compatible = "operating-points-v2"; >>> >>> opp-shared; >> >> Added in v2. >> >>> >>>> + >>>> + opp-75000000 { >>>> + opp-hz = /bits/ 64 <75000000>; >>>> + required-opps = <&rpmhpd_opp_low_svs>; >>>> + }; >>>> + >>>> + opp-100000000 { >>>> + opp-hz = /bits/ 64 <100000000>; >>>> + required-opps = <&rpmhpd_opp_svs>; >>>> + }; >>>> + >>>> + opp-128000000 { >>>> + opp-hz = /bits/ 64 <128000000>; >>>> + required-opps = <&rpmhpd_opp_nom>; >>>> + }; >>>> + }; >>>> + >>>> psci { >>>> compatible = "arm,psci-1.0"; >>>> method = "smc"; >>>> @@ -392,6 +427,24 @@ >>>> #size-cells = <1>; >>>> }; >>>> + gpi_dma0: qcom,gpi-dma@800000 { >>>> + compatible = "qcom,sdm845-gpi-dma"; >>> >>> You must define a new compatible for qcs615, sdm845 is used as a fallback >>> (so that we don't have to add new driver entries). You will however need >>> to submit a separate dt-bindings change. >> >> We have added sdm845 in compatible due to below comment in driver file >> >> File: https://github.com/torvalds/linux/blob/81983758430957d9a5cb3333fe324fd70cf63e7e/drivers/dma/qcom/gpi.c#L2284 >> >> /* >> * Do not grow the list for compatible devices. Instead use >> * qcom,sdm845-gpi-dma (for ee_offset = 0x0) or qcom,sm6350-gpi-dma >> * (for ee_offset = 0x10000). >> */ >> >> Do we still require new compatible for qcs615 ? > > The comment concerns the driver side. All devicetree compatible strings > present in the tree must be documented in Documentation/devicetree/bindings/ > which is where you should add your one as well. > Thanks, Pushed separate patch for GPI documentation patch. https://lore.kernel.org/all/w66ki7lwrqol24iptikn7ccna25ujqoywjena5ulekf6vynxny@dylbj2r34h7l/T/ >> >>> >>>> + reg = <0x0 0x800000 0x0 0x60000>; >>>> + #dma-cells = <3>; >>>> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; >>>> + dma-channels = <8>; >>>> + dma-channel-mask = <0xf>; >>>> + iommus = <&apps_smmu 0xd6 0x0>; >>>> + status = "disabled"; >>> >>> Any reason? >> >> By default, we are disabling all nodes. In the target-specific file, we will update them based on the required use case. >> >>> >>>> + }; >>>> + >>>> qupv3_id_0: geniqup@8c0000 { >>>> compatible = "qcom,geni-se-qup"; >>>> reg = <0x0 0x8c0000 0x0 0x6000>; >>>> @@ -400,6 +453,7 @@ >>>> <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; >>>> clock-names = "m-ahb", >>>> "s-ahb"; >>>> + iommus = <&apps_smmu 0xc3 0x0>; >>> >>> This looks like a separate fix >> >> One QUP and UART (console) related change has been added as part of the base DTSI. Now, we are adding all remaining QUP and I2C/SPI/UART configurations with IOMMUs and other properties. >> >> Is there any specific reason to make this a separate fix? > > Did this work properly before? Earlier, we verified the console UART use case, and it worked. > > Konrad
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index 865ead601f85..9d7fc6fc5c6e 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/clock/qcom,qcs615-gcc.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -17,6 +18,21 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + spi2 = &spi2; + spi4 = &spi4; + spi6 = &spi6; + spi7 = &spi7; + serial0 = &uart0; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -296,6 +312,25 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -392,6 +427,24 @@ #size-cells = <1>; }; + gpi_dma0: qcom,gpi-dma@800000 { + compatible = "qcom,sdm845-gpi-dma"; + reg = <0x0 0x800000 0x0 0x60000>; + #dma-cells = <3>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <8>; + dma-channel-mask = <0xf>; + iommus = <&apps_smmu 0xd6 0x0>; + status = "disabled"; + }; + qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x8c0000 0x0 0x6000>; @@ -400,6 +453,7 @@ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0xc3 0x0>; #address-cells = <2>; #size-cells = <2>; status = "disabled"; @@ -412,13 +466,377 @@ pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>; pinctrl-names = "default"; interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; - interconnects = <&aggre1_noc MASTER_QUP_0 0 - &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 - &config_noc SLAVE_QUP_0 0>; + interconnects = <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + status = "disabled"; + }; + + i2c1: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x884000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + interconnects = <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + i2c2: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x888000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + interconnects = <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi2: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + interconnects = <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart2: serial@888000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, + <&qup_uart2_tx>, <&qup_uart2_rx>; + pinctrl-names = "default"; + interconnects = <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + status = "disabled"; + }; + + i2c3: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x88c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + interconnects = <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + }; + + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,sdm845-gpi-dma"; + reg = <0x0 0xa00000 0x0 0x60000>; + #dma-cells = <3>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <8>; + dma-channel-mask = <0xf>; + iommus = <&apps_smmu 0x376 0x0>; + status = "disabled"; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0xac0000 0x0 0x2000>; + ranges; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + iommus = <&apps_smmu 0x363 0x0>; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + i2c4: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa80000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c4_data_clk>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi4: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa80000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart4: serial@a80000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa80000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, + <&qup_uart4_tx>, <&qup_uart4_rx>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + + i2c5: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa84000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c5_data_clk>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + i2c6: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa88000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c6_data_clk>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi6: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa88000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart6: serial@a88000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa88000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, + <&qup_uart6_tx>, <&qup_uart6_rx>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + + i2c7: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa8c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c7_data_clk>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi7: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa8c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart7: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa8c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, + <&qup_uart7_tx>, <&qup_uart7_rx>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; }; @@ -478,6 +896,102 @@ #interrupt-cells = <2>; wakeup-parent = <&pdc>; + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + pins = "gpio4", "gpio5"; + function = "qup0"; + + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + pins = "gpio0", "gpio1"; + function = "qup0"; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + pins = "gpio18", "gpio19"; + function = "qup0"; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + pins = "gpio20", "gpio21"; + function = "qup1"; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + pins = "gpio14", "gpio15"; + function = "qup1"; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + pins = "gpio6", "gpio7"; + function = "qup1"; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + pins = "gpio10", "gpio11"; + function = "qup1"; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + pins = "gpio0", "gpio1", "gpio2"; + function = "qup0"; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio3"; + function = "qup0"; + }; + + qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { + pins = "gpio3"; + function = "gpio"; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + pins = "gpio20", "gpio21", "gpio22"; + function = "qup1"; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio23"; + function = "qup1"; + }; + + qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { + pins = "gpio23"; + function = "gpio"; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + pins = "gpio6", "gpio7", "gpio8"; + function = "qup1"; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio9"; + function = "qup1"; + }; + + qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { + pins = "gpio9"; + function = "gpio"; + }; + + qup_spi7_data_clk: qup-spi7-data-clk-state { + pins = "gpio10", "gpio11", "gpio12"; + function = "qup1"; + }; + + qup_spi7_cs: qup-spi7-cs-state { + pins = "gpio13"; + function = "qup1"; + }; + + qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { + pins = "gpio13"; + function = "gpio"; + }; + qup_uart0_tx: qup-uart0-tx-state { pins = "gpio16"; function = "qup0"; @@ -487,6 +1001,86 @@ pins = "gpio17"; function = "qup0"; }; + + qup_uart2_cts: qup-uart2-cts-state { + pins = "gpio0"; + function = "qup0"; + }; + + qup_uart2_rts: qup-uart2-rts-state { + pins = "gpio1"; + function = "qup0"; + }; + + qup_uart2_tx: qup-uart2-tx-state { + pins = "gpio2"; + function = "qup0"; + }; + + qup_uart2_rx: qup-uart2-rx-state { + pins = "gpio3"; + function = "qup0"; + }; + + qup_uart4_cts: qup-uart4-cts-state { + pins = "gpio20"; + function = "qup1"; + }; + + qup_uart4_rts: qup-uart4-rts-state { + pins = "gpio21"; + function = "qup1"; + }; + + qup_uart4_tx: qup-uart4-tx-state { + pins = "gpio22"; + function = "qup1"; + }; + + qup_uart4_rx: qup-uart4-rx-state { + pins = "gpio23"; + function = "qup1"; + }; + + qup_uart6_cts: qup-uart6-cts-state { + pins = "gpio6"; + function = "qup1"; + }; + + qup_uart6_rts: qup-uart6-rts-state { + pins = "gpio7"; + function = "qup1"; + }; + + qup_uart6_tx: qup-uart6-tx-state { + pins = "gpio8"; + function = "qup1"; + }; + + qup_uart6_rx: qup-uart6-rx-state { + pins = "gpio9"; + function = "qup1"; + }; + + qup_uart7_cts: qup-uart7-cts-state { + pins = "gpio10"; + function = "qup1"; + }; + + qup_uart7_rts: qup-uart7-rts-state { + pins = "gpio11"; + function = "qup1"; + }; + + qup_uart7_tx: qup-uart7-tx-state { + pins = "gpio12"; + function = "qup1"; + }; + + qup_uart7_rx: qup-uart7-rx-state { + pins = "gpio13"; + function = "qup1"; + }; }; dc_noc: interconnect@9160000 {