| Message ID | cover.1729807947.git.babu.moger@amd.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | target/i386: Add support for perfmon-v2, RAS bits and EPYC-Turin CPU model | expand |
On 10/25/24 00:18, Babu Moger wrote: > > This series adds the support for following features in qemu. > 1. RAS feature bits (SUCCOR, McaOverflowRecov) > 2. perfmon-v2 > 3. Update EPYC-Genoa to support perfmon-v2 and RAS bits > 4. Support for bits related to SRSO (sbpb, ibpb-brtype, srso-user-kernel-no) > 5. Added support for feature bits CPUID_Fn80000021_EAX/CPUID_Fn80000021_EBX > to address CPUID enforcement requirement in Turin platforms. > 6. Add support for EPYC-Turin. Queued, thanks. I looked at https://gitlab.com/qemu-project/qemu/-/issues/2571 and I think it's caused by the ignore_msrs=1 parameter on the KVM kernel module. However, can you look into adding new CPUID_SVM_* bits? Thanks, Paolo > Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip > Link: https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf > --- > v3: Added SBPB, IBPB_BRTYPE, SRSO_USER_KERNEL_NO, ERAPS and RAPSIZE bits > to EPYC-Turin. > > v2: Fixed couple of typos. > Added Reviewed-by tag from Zhao. > Rebased on top of 6d00c6f98256 ("Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into staging") > > v2: https://lore.kernel.org/kvm/cover.1723068946.git.babu.moger@amd.com/ > > v1: https://lore.kernel.org/qemu-devel/cover.1718218999.git.babu.moger@amd.com/ > > Babu Moger (6): > target/i386: Fix minor typo in NO_NESTED_DATA_BP feature bit > target/i386: Add RAS feature bits on EPYC CPU models > target/i386: Enable perfmon-v2 and RAS feature bits on EPYC-Genoa > target/i386: Expose bits related to SRSO vulnerability > target/i386: Expose new feature bits in CPUID 8000_0021_EAX/EBX > target/i386: Add support for EPYC-Turin model > > Sandipan Das (1): > target/i386: Add PerfMonV2 feature bit > > target/i386/cpu.c | 222 +++++++++++++++++++++++++++++++++++++++++++++- > target/i386/cpu.h | 27 +++++- > 2 files changed, 242 insertions(+), 7 deletions(-) >
Hi Paolo, On 10/28/24 03:37, Paolo Bonzini wrote: > On 10/25/24 00:18, Babu Moger wrote: >> >> This series adds the support for following features in qemu. >> 1. RAS feature bits (SUCCOR, McaOverflowRecov) >> 2. perfmon-v2 >> 3. Update EPYC-Genoa to support perfmon-v2 and RAS bits >> 4. Support for bits related to SRSO (sbpb, ibpb-brtype, >> srso-user-kernel-no) >> 5. Added support for feature bits CPUID_Fn80000021_EAX/CPUID_Fn80000021_EBX >> to address CPUID enforcement requirement in Turin platforms. >> 6. Add support for EPYC-Turin. > > Queued, thanks. I looked at Thanks. > https://gitlab.com/qemu-project/qemu/-/issues/2571 and I think it's caused > by the ignore_msrs=1 parameter on the KVM kernel module. Thanks again. > > However, can you look into adding new CPUID_SVM_* bits? I normally pickup bits when it is added in kernel/kvm. Are you thinking of any specific bits here? Thanks Babu
On Mon, Oct 28, 2024 at 3:23 PM Moger, Babu <babu.moger@amd.com> wrote: > > Hi Paolo, > > On 10/28/24 03:37, Paolo Bonzini wrote: > > On 10/25/24 00:18, Babu Moger wrote: > >> > >> This series adds the support for following features in qemu. > >> 1. RAS feature bits (SUCCOR, McaOverflowRecov) > >> 2. perfmon-v2 > >> 3. Update EPYC-Genoa to support perfmon-v2 and RAS bits > >> 4. Support for bits related to SRSO (sbpb, ibpb-brtype, > >> srso-user-kernel-no) > >> 5. Added support for feature bits CPUID_Fn80000021_EAX/CPUID_Fn80000021_EBX > >> to address CPUID enforcement requirement in Turin platforms. > >> 6. Add support for EPYC-Turin. > > > > Queued, thanks. I looked at > > Thanks. > > > https://gitlab.com/qemu-project/qemu/-/issues/2571 and I think it's caused > > by the ignore_msrs=1 parameter on the KVM kernel module. > > Thanks again. > > > > > However, can you look into adding new CPUID_SVM_* bits? > > I normally pickup bits when it is added in kernel/kvm. Are you thinking of > any specific bits here? Yes, KVM already supports vGIF, virtual VMLOAD/VMSAVE, virtual TSC rate MSR, vNMI, virtual LBR, virtual pause filter and virtual pause filter threshold. Paolo
On 10/28/24 09:25, Paolo Bonzini wrote: > On Mon, Oct 28, 2024 at 3:23 PM Moger, Babu <babu.moger@amd.com> wrote: >> >> Hi Paolo, >> >> On 10/28/24 03:37, Paolo Bonzini wrote: >>> On 10/25/24 00:18, Babu Moger wrote: >>>> >>>> This series adds the support for following features in qemu. >>>> 1. RAS feature bits (SUCCOR, McaOverflowRecov) >>>> 2. perfmon-v2 >>>> 3. Update EPYC-Genoa to support perfmon-v2 and RAS bits >>>> 4. Support for bits related to SRSO (sbpb, ibpb-brtype, >>>> srso-user-kernel-no) >>>> 5. Added support for feature bits CPUID_Fn80000021_EAX/CPUID_Fn80000021_EBX >>>> to address CPUID enforcement requirement in Turin platforms. >>>> 6. Add support for EPYC-Turin. >>> >>> Queued, thanks. I looked at >> >> Thanks. >> >>> https://gitlab.com/qemu-project/qemu/-/issues/2571 and I think it's caused >>> by the ignore_msrs=1 parameter on the KVM kernel module. >> >> Thanks again. >> >>> >>> However, can you look into adding new CPUID_SVM_* bits? >> >> I normally pickup bits when it is added in kernel/kvm. Are you thinking of >> any specific bits here? > > Yes, KVM already supports vGIF, virtual VMLOAD/VMSAVE, virtual TSC > rate MSR, vNMI, virtual LBR, virtual pause filter and virtual pause > filter threshold. Oh ok. Sure. I will look into this.
On 10/25/24 00:18, Babu Moger wrote: > > This series adds the support for following features in qemu. > 1. RAS feature bits (SUCCOR, McaOverflowRecov) > 2. perfmon-v2 > 3. Update EPYC-Genoa to support perfmon-v2 and RAS bits > 4. Support for bits related to SRSO (sbpb, ibpb-brtype, srso-user-kernel-no) > 5. Added support for feature bits CPUID_Fn80000021_EAX/CPUID_Fn80000021_EBX > to address CPUID enforcement requirement in Turin platforms. > 6. Add support for EPYC-Turin. Queued the following - target/i386: Fix minor typo in NO_NESTED_DATA_BP feature bit - target/i386: Add PerfMonV2 feature bit - target/i386: Expose bits related to SRSO vulnerability - target/i386: Expose new feature bits in CPUID 8000_0021_EAX/EBX I am leaving out the CPU model updates so that they are updated just once instead of twice (especially Turin should have the right CPUID bits for nested SVM). Paolo
This series adds the support for following features in qemu. 1. RAS feature bits (SUCCOR, McaOverflowRecov) 2. perfmon-v2 3. Update EPYC-Genoa to support perfmon-v2 and RAS bits 4. Support for bits related to SRSO (sbpb, ibpb-brtype, srso-user-kernel-no) 5. Added support for feature bits CPUID_Fn80000021_EAX/CPUID_Fn80000021_EBX to address CPUID enforcement requirement in Turin platforms. 6. Add support for EPYC-Turin. Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip Link: https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf --- v3: Added SBPB, IBPB_BRTYPE, SRSO_USER_KERNEL_NO, ERAPS and RAPSIZE bits to EPYC-Turin. v2: Fixed couple of typos. Added Reviewed-by tag from Zhao. Rebased on top of 6d00c6f98256 ("Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into staging") v2: https://lore.kernel.org/kvm/cover.1723068946.git.babu.moger@amd.com/ v1: https://lore.kernel.org/qemu-devel/cover.1718218999.git.babu.moger@amd.com/ Babu Moger (6): target/i386: Fix minor typo in NO_NESTED_DATA_BP feature bit target/i386: Add RAS feature bits on EPYC CPU models target/i386: Enable perfmon-v2 and RAS feature bits on EPYC-Genoa target/i386: Expose bits related to SRSO vulnerability target/i386: Expose new feature bits in CPUID 8000_0021_EAX/EBX target/i386: Add support for EPYC-Turin model Sandipan Das (1): target/i386: Add PerfMonV2 feature bit target/i386/cpu.c | 222 +++++++++++++++++++++++++++++++++++++++++++++- target/i386/cpu.h | 27 +++++- 2 files changed, 242 insertions(+), 7 deletions(-)