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[5.10.y-cip,17/27] media: platform: rzg2l-cru: rzg2l-csi2: Enclose the macro in parentheses

Message ID 20241028200349.9620-18-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State New
Headers show
Series Add CRU and CSI support for Renesas RZ/G2L | expand

Commit Message

Lad Prabhakar Oct. 28, 2024, 8:03 p.m. UTC 
commit e5f29bb9c4350dd9692f3b98eb8538dbbebccbaf upstream.

Fix the below error reported by checkpatch:

ERROR: Macros with complex values should be enclosed in parentheses
					CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(1) | \
					CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(1) | \
					CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(1)

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Pavel Machek Oct. 30, 2024, 10:52 a.m. UTC | #1 
Hi!

> commit e5f29bb9c4350dd9692f3b98eb8538dbbebccbaf upstream.
> 
> Fix the below error reported by checkpatch:

I don't see this one in 6.1-cip. Can you submit it for that branch,
too?

(Are there others that are missing from 6.1?)

Best regards,
								Pavel
diff mbox series

Patch

diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
index b413ad7ff6388..3f874edcabed8 100644
--- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
+++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
@@ -81,10 +81,10 @@ 
 #define CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(x)	(((x) & 0x3) << 4)
 #define CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(x)	(((x) & 0x3) << 8)
 #define CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(x)	(((x) & 0x3) << 12)
-#define CSIDPHYSKW0_DEFAULT_SKW		CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(1) | \
-					CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(1) | \
-					CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(1) | \
-					CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(1)
+#define CSIDPHYSKW0_DEFAULT_SKW		(CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(1) | \
+					 CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(1) | \
+					 CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(1) | \
+					 CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(1))
 
 #define VSRSTS_RETRIES			20