| Message ID | 20241025131442.112862-9-peter.griffin@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | UFS cleanups and enhancements to ufs-exynos for gs101 | expand |
On 10/25/24 2:14 PM, Peter Griffin wrote: > Previously just AXIDMA_RWDATA_BURST_LEN[3:0] field was set to 8. where was this set? > > To enable WLU transaction additionally we need to set Write Line > Unique enable [31], Write Line Unique Burst Length [30:27] and > AXIDMA_RWDATA_BURST_LEN[3:0]. > > To support WLU transaction, both burth length fields need to be 0x3. > typo, s/burth/burst
Hi Tudor, On Wed, 30 Oct 2024 at 11:25, Tudor Ambarus <tudor.ambarus@linaro.org> wrote: > > > > On 10/25/24 2:14 PM, Peter Griffin wrote: > > Previously just AXIDMA_RWDATA_BURST_LEN[3:0] field was set to 8. > > where was this set? It is set to 0xf in exynos_ufs_post_link() function, see the following line hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN); As all other SoCs expect the current value, I've left that assignment in the common function, and we update it in the gs101_ufs_post_link() specific hook. > > > > > To enable WLU transaction additionally we need to set Write Line > > Unique enable [31], Write Line Unique Burst Length [30:27] and > > AXIDMA_RWDATA_BURST_LEN[3:0]. > > > > To support WLU transaction, both burth length fields need to be 0x3. > > > > typo, s/burth/burst Will fix. Peter
On 10/30/24 11:32 AM, Peter Griffin wrote: >>> Previously just AXIDMA_RWDATA_BURST_LEN[3:0] field was set to 8. >> where was this set? > It is set to 0xf in exynos_ufs_post_link() function, see the following line > hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN); > > As all other SoCs expect the current value, I've left that assignment > in the common function, and we update it in the gs101_ufs_post_link() > specific hook. > oh yes, as a driver quirk. Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 40b2563fe011..b0cbb147c7a1 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -48,6 +48,8 @@ #define HCI_UNIPRO_APB_CLK_CTRL 0x68 #define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF)) #define HCI_AXIDMA_RWDATA_BURST_LEN 0x6C +#define WLU_EN BIT(31) +#define WLU_BURST_LEN(x) ((x) << 27 | ((x) & 0xF)) #define HCI_GPIO_OUT 0x70 #define HCI_ERR_EN_PA_LAYER 0x78 #define HCI_ERR_EN_DL_LAYER 0x7C @@ -1925,6 +1927,12 @@ static int gs101_ufs_post_link(struct exynos_ufs *ufs) { struct ufs_hba *hba = ufs->hba; + /* + * Enable Write Line Unique. This field has to be 0x3 + * to support Write Line Unique transaction on gs101. + */ + hci_writel(ufs, WLU_EN | WLU_BURST_LEN(3), HCI_AXIDMA_RWDATA_BURST_LEN); + exynos_ufs_enable_dbg_mode(hba); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0x3e8); exynos_ufs_disable_dbg_mode(hba);
Previously just AXIDMA_RWDATA_BURST_LEN[3:0] field was set to 8. To enable WLU transaction additionally we need to set Write Line Unique enable [31], Write Line Unique Burst Length [30:27] and AXIDMA_RWDATA_BURST_LEN[3:0]. To support WLU transaction, both burth length fields need to be 0x3. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> --- drivers/ufs/host/ufs-exynos.c | 8 ++++++++ 1 file changed, 8 insertions(+)