| Message ID | 63d01f172cabd5a7741434fb923ed7e1447776ee.1729807947.git.babu.moger@amd.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | target/i386: Add support for perfmon-v2, RAS bits and EPYC-Turin CPU model | expand |
(+John) Hi Babu, This patch is fine for me. However, users recently reported an issue with SUCCOR support on AMD hosts: https://gitlab.com/qemu-project/qemu/-/issues/2571. Could you please double check and clarify that issue on AMD host? Thanks, Zhao On Thu, Oct 24, 2024 at 05:18:20PM -0500, Babu Moger wrote: > Date: Thu, 24 Oct 2024 17:18:20 -0500 > From: Babu Moger <babu.moger@amd.com> > Subject: [PATCH v3 2/7] target/i386: Add RAS feature bits on EPYC CPU models > X-Mailer: git-send-email 2.34.1 > > Add the support for following RAS features bits on AMD guests. > > SUCCOR: Software uncorrectable error containment and recovery capability. > The processor supports software containment of uncorrectable errors > through context synchronizing data poisoning and deferred error > interrupts. > > McaOverflowRecov: MCA overflow recovery support. > > Reviewed-by: Zhao Liu <zhao1.liu@intel.com> > Signed-off-by: Babu Moger <babu.moger@amd.com> > --- > v3: No changes > > v2: Added reviewed by from Zhao. > --- > target/i386/cpu.c | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+)
On Mon, Oct 28, 2024 at 02:59:17PM +0800, Zhao Liu wrote: > (+John) > > Hi Babu, > > This patch is fine for me. > > However, users recently reported an issue with SUCCOR support on AMD > hosts: https://gitlab.com/qemu-project/qemu/-/issues/2571. > > Could you please double check and clarify that issue on AMD host? Thanks for the heads up. I can reproduce this on an AMD host with kvm.ignore_msrs=1. It seems like kvm will need to block this feature on the guest when ignore_msrs is set, but it's not clear to me how that should be done yet. Paolo, Do you have any ideas about how we should handle this situation? Thanks, John > > Thanks, > Zhao > > On Thu, Oct 24, 2024 at 05:18:20PM -0500, Babu Moger wrote: > > Date: Thu, 24 Oct 2024 17:18:20 -0500 > > From: Babu Moger <babu.moger@amd.com> > > Subject: [PATCH v3 2/7] target/i386: Add RAS feature bits on EPYC CPU models > > X-Mailer: git-send-email 2.34.1 > > > > Add the support for following RAS features bits on AMD guests. > > > > SUCCOR: Software uncorrectable error containment and recovery capability. > > The processor supports software containment of uncorrectable errors > > through context synchronizing data poisoning and deferred error > > interrupts. > > > > McaOverflowRecov: MCA overflow recovery support. > > > > Reviewed-by: Zhao Liu <zhao1.liu@intel.com> > > Signed-off-by: Babu Moger <babu.moger@amd.com> > > --- > > v3: No changes > > > > v2: Added reviewed by from Zhao. > > --- > > target/i386/cpu.c | 30 ++++++++++++++++++++++++++++++ > > 1 file changed, 30 insertions(+) >
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 94faff83cd..e88859056a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4974,6 +4974,16 @@ static const X86CPUDefinition builtin_x86_defs[] = { }, .cache_info = &epyc_v4_cache_info }, + { + .version = 5, + .props = (PropValue[]) { + { "overflow-recov", "on" }, + { "succor", "on" }, + { "model-id", + "AMD EPYC-v5 Processor" }, + { /* end of list */ } + }, + }, { /* end of list */ } } }, @@ -5112,6 +5122,16 @@ static const X86CPUDefinition builtin_x86_defs[] = { { /* end of list */ } }, }, + { + .version = 5, + .props = (PropValue[]) { + { "overflow-recov", "on" }, + { "succor", "on" }, + { "model-id", + "AMD EPYC-Rome-v5 Processor" }, + { /* end of list */ } + }, + }, { /* end of list */ } } }, @@ -5187,6 +5207,16 @@ static const X86CPUDefinition builtin_x86_defs[] = { }, .cache_info = &epyc_milan_v2_cache_info }, + { + .version = 3, + .props = (PropValue[]) { + { "overflow-recov", "on" }, + { "succor", "on" }, + { "model-id", + "AMD EPYC-Milan-v3 Processor" }, + { /* end of list */ } + }, + }, { /* end of list */ } } },