| Message ID | 20241031114027.225217-1-mika.kahola@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | drm/i915/display: Power request asserting/deasserting | expand |
On Thu, Oct 31, 2024 at 01:40:25PM +0200, Mika Kahola wrote: > There is a HW issue that arises when there are race conditions > between TCSS entering/exiting TC7 or TC10 states while the > driver is asserting/deasserting TCSS power request. As a > workaround, Display driver will implement a mailbox sequence > to ensure that the TCSS is in TC0 when TCSS power request is > asserted/deasserted. > > The sequence is the following > > 1. Read mailbox command status and wait until run/busy bit is > clear > 2. Write mailbox data value '1' for power request asserting > and '0' for power request deasserting > 3. Write mailbox command run/busy bit and command value with 0x1 > 4. Read mailbox command and wait until run/busy bit is clear > before continuing power request. > > while at it, let's start using struct intel_display instead of > struct drm_i915_private as well. Perhaps this needs to be its own patch since it's unrelated to the series. Raag
> -----Original Message----- > From: Jadav, Raag <raag.jadav@intel.com> > Sent: Thursday, 31 October 2024 14.59 > To: Kahola, Mika <mika.kahola@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Sousa, Gustavo <gustavo.sousa@intel.com>; > jani.nikula@linux.intel.com > Subject: Re: [PATCH v3 0/2] drm/i915/display: Power request > asserting/deasserting > > On Thu, Oct 31, 2024 at 01:40:25PM +0200, Mika Kahola wrote: > > There is a HW issue that arises when there are race conditions between > > TCSS entering/exiting TC7 or TC10 states while the driver is > > asserting/deasserting TCSS power request. As a workaround, Display > > driver will implement a mailbox sequence to ensure that the TCSS is in > > TC0 when TCSS power request is asserted/deasserted. > > > > The sequence is the following > > > > 1. Read mailbox command status and wait until run/busy bit is > > clear > > 2. Write mailbox data value '1' for power request asserting > > and '0' for power request deasserting 3. Write mailbox command > > run/busy bit and command value with 0x1 4. Read mailbox command and > > wait until run/busy bit is clear > > before continuing power request. > > > > while at it, let's start using struct intel_display instead of struct > > drm_i915_private as well. > > Perhaps this needs to be its own patch since it's unrelated to the series. There was a request from Jani to start using intel_display instead of drm_i915_private also with the calling function. So this is perhaps remotely related to this WA I included this here. > > Raag
On Thu, Oct 31, 2024 at 07:58:19PM +0530, Kahola, Mika wrote: > > -----Original Message----- > > From: Jadav, Raag <raag.jadav@intel.com> > > Sent: Thursday, 31 October 2024 14.59 > > To: Kahola, Mika <mika.kahola@intel.com> > > Cc: intel-gfx@lists.freedesktop.org; Sousa, Gustavo <gustavo.sousa@intel.com>; > > jani.nikula@linux.intel.com > > Subject: Re: [PATCH v3 0/2] drm/i915/display: Power request > > asserting/deasserting > > > > On Thu, Oct 31, 2024 at 01:40:25PM +0200, Mika Kahola wrote: > > > There is a HW issue that arises when there are race conditions between > > > TCSS entering/exiting TC7 or TC10 states while the driver is > > > asserting/deasserting TCSS power request. As a workaround, Display > > > driver will implement a mailbox sequence to ensure that the TCSS is in > > > TC0 when TCSS power request is asserted/deasserted. > > > > > > The sequence is the following > > > > > > 1. Read mailbox command status and wait until run/busy bit is > > > clear > > > 2. Write mailbox data value '1' for power request asserting > > > and '0' for power request deasserting 3. Write mailbox command > > > run/busy bit and command value with 0x1 4. Read mailbox command and > > > wait until run/busy bit is clear > > > before continuing power request. > > > > > > while at it, let's start using struct intel_display instead of struct > > > drm_i915_private as well. > > > > Perhaps this needs to be its own patch since it's unrelated to the series. > > There was a request from Jani to start using intel_display instead of > drm_i915_private also with the calling function. So this is perhaps > remotely related to this WA I included this here. Yes, he has a series WIP for it. Perhaps worth collaborating. Raag
There is a HW issue that arises when there are race conditions between TCSS entering/exiting TC7 or TC10 states while the driver is asserting/deasserting TCSS power request. As a workaround, Display driver will implement a mailbox sequence to ensure that the TCSS is in TC0 when TCSS power request is asserted/deasserted. The sequence is the following 1. Read mailbox command status and wait until run/busy bit is clear 2. Write mailbox data value '1' for power request asserting and '0' for power request deasserting 3. Write mailbox command run/busy bit and command value with 0x1 4. Read mailbox command and wait until run/busy bit is clear before continuing power request. while at it, let's start using struct intel_display instead of struct drm_i915_private as well. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Mika Kahola (2): drm/i915/xe3lpd: Power request asserting/deasserting drm/i915/display: Use struct intel_display instead of struct drm_i915_private .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 8 ++++ drivers/gpu/drm/i915/display/intel_tc.c | 45 +++++++++++++++++-- 2 files changed, 49 insertions(+), 4 deletions(-)