| Message ID | 20241025210305.27499-4-terry.bowman@amd.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enable CXL PCIe port protocol error handling and logging | expand |
On Fri, 25 Oct 2024 16:02:54 -0500 Terry Bowman <terry.bowman@amd.com> wrote: > CXL and AER drivers need the ability to identify CXL devices and CXL port > devices. > > First, add set_pcie_cxl() with logic checking for CXL Flexbus DVSEC > presence. The CXL Flexbus DVSEC presence is used because it is required > for all the CXL PCIe devices.[1] > > Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL > Flexbus presence. > > Add pcie_is_cxl() as a macro to return 'struct pci_dev::is_cxl', > > Add pcie_is_cxl_port() to check if a device is a CXL root port, CXL > upstream switch port, or CXL downstream switch port. Also, verify the > CXL extensions DVSEC for port is present.[1] > > [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended > Capability (DVSEC) ID Assignment, Table 8-2 > > Signed-off-by: Terry Bowman <terry.bowman@amd.com> Make sense to improve the trace point info if nothing else. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
On 10/25/24 2:02 PM, Terry Bowman wrote: > CXL and AER drivers need the ability to identify CXL devices and CXL port > devices. > > First, add set_pcie_cxl() with logic checking for CXL Flexbus DVSEC > presence. The CXL Flexbus DVSEC presence is used because it is required > for all the CXL PCIe devices.[1] > > Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL > Flexbus presence. > > Add pcie_is_cxl() as a macro to return 'struct pci_dev::is_cxl', > > Add pcie_is_cxl_port() to check if a device is a CXL root port, CXL > upstream switch port, or CXL downstream switch port. Also, verify the > CXL extensions DVSEC for port is present.[1] > > [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended > Capability (DVSEC) ID Assignment, Table 8-2 > > Signed-off-by: Terry Bowman <terry.bowman@amd.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> > --- > drivers/pci/pci.c | 14 ++++++++++++++ > drivers/pci/probe.c | 10 ++++++++++ > include/linux/pci.h | 4 ++++ > include/uapi/linux/pci_regs.h | 3 ++- > 4 files changed, 30 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index 7d85c04fbba2..c1b243aec61c 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -5034,6 +5034,20 @@ static u16 cxl_port_dvsec(struct pci_dev *dev) > PCI_DVSEC_CXL_PORT); > } > > +bool pcie_is_cxl_port(struct pci_dev *dev) > +{ > + if (!pcie_is_cxl(dev)) > + return false; > + > + if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && > + (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) && > + (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)) > + return false; > + > + return cxl_port_dvsec(dev); > +} > +EXPORT_SYMBOL_GPL(pcie_is_cxl_port); > + > static bool cxl_sbr_masked(struct pci_dev *dev) > { > u16 dvsec, reg; > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c > index 4f68414c3086..9324eb345f11 100644 > --- a/drivers/pci/probe.c > +++ b/drivers/pci/probe.c > @@ -1631,6 +1631,14 @@ static void set_pcie_thunderbolt(struct pci_dev *dev) > dev->is_thunderbolt = 1; > } > > +static void set_pcie_cxl(struct pci_dev *dev) > +{ > + u16 dvsec = pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, > + PCI_DVSEC_CXL_FLEXBUS); > + if (dvsec) > + dev->is_cxl = 1; > +} > + > static void set_pcie_untrusted(struct pci_dev *dev) > { > struct pci_dev *parent; > @@ -1945,6 +1953,8 @@ int pci_setup_device(struct pci_dev *dev) > /* Need to have dev->cfg_size ready */ > set_pcie_thunderbolt(dev); > > + set_pcie_cxl(dev); > + > set_pcie_untrusted(dev); > > /* "Unknown power state" */ > diff --git a/include/linux/pci.h b/include/linux/pci.h > index 106ac83e3a7b..d3b1af9fb273 100644 > --- a/include/linux/pci.h > +++ b/include/linux/pci.h > @@ -443,6 +443,7 @@ struct pci_dev { > unsigned int is_hotplug_bridge:1; > unsigned int shpc_managed:1; /* SHPC owned by shpchp */ > unsigned int is_thunderbolt:1; /* Thunderbolt controller */ > + unsigned int is_cxl:1; /* CXL alternate protocol */ > /* > * Devices marked being untrusted are the ones that can potentially > * execute DMA attacks and similar. They are typically connected > @@ -743,6 +744,9 @@ static inline bool pci_is_vga(struct pci_dev *pdev) > return false; > } > > +#define pcie_is_cxl(dev) (dev->is_cxl) > +bool pcie_is_cxl_port(struct pci_dev *dev); > + > #define for_each_pci_bridge(dev, bus) \ > list_for_each_entry(dev, &bus->devices, bus_list) \ > if (!pci_is_bridge(dev)) {} else > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index 12323b3334a9..5df6c74963c5 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -1186,9 +1186,10 @@ > #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000 > #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000 > > -/* Compute Express Link (CXL r3.1, sec 8.1.5) */ > +/* Compute Express Link (CXL r3.1, sec 8.1) */ > #define PCI_DVSEC_CXL_PORT 3 > #define PCI_DVSEC_CXL_PORT_CTL 0x0c > #define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 > +#define PCI_DVSEC_CXL_FLEXBUS 7 > > #endif /* LINUX_PCI_REGS_H */
On Fri, Oct 25, 2024 at 04:02:54PM -0500, Terry Bowman wrote: > CXL and AER drivers need the ability to identify CXL devices and CXL port > devices. > > First, add set_pcie_cxl() with logic checking for CXL Flexbus DVSEC > presence. The CXL Flexbus DVSEC presence is used because it is required > for all the CXL PCIe devices.[1] > > Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL > Flexbus presence. > > Add pcie_is_cxl() as a macro to return 'struct pci_dev::is_cxl', > > Add pcie_is_cxl_port() to check if a device is a CXL root port, CXL > upstream switch port, or CXL downstream switch port. Also, verify the > CXL extensions DVSEC for port is present.[1] > > [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended > Capability (DVSEC) ID Assignment, Table 8-2 > > Signed-off-by: Terry Bowman <terry.bowman@amd.com> > --- Reviewed-by: Fan Ni <fan.ni@samsung.com> > drivers/pci/pci.c | 14 ++++++++++++++ > drivers/pci/probe.c | 10 ++++++++++ > include/linux/pci.h | 4 ++++ > include/uapi/linux/pci_regs.h | 3 ++- > 4 files changed, 30 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index 7d85c04fbba2..c1b243aec61c 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -5034,6 +5034,20 @@ static u16 cxl_port_dvsec(struct pci_dev *dev) > PCI_DVSEC_CXL_PORT); > } > > +bool pcie_is_cxl_port(struct pci_dev *dev) > +{ > + if (!pcie_is_cxl(dev)) > + return false; > + > + if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && > + (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) && > + (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)) > + return false; > + > + return cxl_port_dvsec(dev); > +} > +EXPORT_SYMBOL_GPL(pcie_is_cxl_port); > + > static bool cxl_sbr_masked(struct pci_dev *dev) > { > u16 dvsec, reg; > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c > index 4f68414c3086..9324eb345f11 100644 > --- a/drivers/pci/probe.c > +++ b/drivers/pci/probe.c > @@ -1631,6 +1631,14 @@ static void set_pcie_thunderbolt(struct pci_dev *dev) > dev->is_thunderbolt = 1; > } > > +static void set_pcie_cxl(struct pci_dev *dev) > +{ > + u16 dvsec = pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, > + PCI_DVSEC_CXL_FLEXBUS); > + if (dvsec) > + dev->is_cxl = 1; > +} > + > static void set_pcie_untrusted(struct pci_dev *dev) > { > struct pci_dev *parent; > @@ -1945,6 +1953,8 @@ int pci_setup_device(struct pci_dev *dev) > /* Need to have dev->cfg_size ready */ > set_pcie_thunderbolt(dev); > > + set_pcie_cxl(dev); > + > set_pcie_untrusted(dev); > > /* "Unknown power state" */ > diff --git a/include/linux/pci.h b/include/linux/pci.h > index 106ac83e3a7b..d3b1af9fb273 100644 > --- a/include/linux/pci.h > +++ b/include/linux/pci.h > @@ -443,6 +443,7 @@ struct pci_dev { > unsigned int is_hotplug_bridge:1; > unsigned int shpc_managed:1; /* SHPC owned by shpchp */ > unsigned int is_thunderbolt:1; /* Thunderbolt controller */ > + unsigned int is_cxl:1; /* CXL alternate protocol */ > /* > * Devices marked being untrusted are the ones that can potentially > * execute DMA attacks and similar. They are typically connected > @@ -743,6 +744,9 @@ static inline bool pci_is_vga(struct pci_dev *pdev) > return false; > } > > +#define pcie_is_cxl(dev) (dev->is_cxl) > +bool pcie_is_cxl_port(struct pci_dev *dev); > + > #define for_each_pci_bridge(dev, bus) \ > list_for_each_entry(dev, &bus->devices, bus_list) \ > if (!pci_is_bridge(dev)) {} else > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index 12323b3334a9..5df6c74963c5 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -1186,9 +1186,10 @@ > #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000 > #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000 > > -/* Compute Express Link (CXL r3.1, sec 8.1.5) */ > +/* Compute Express Link (CXL r3.1, sec 8.1) */ > #define PCI_DVSEC_CXL_PORT 3 > #define PCI_DVSEC_CXL_PORT_CTL 0x0c > #define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 > +#define PCI_DVSEC_CXL_FLEXBUS 7 > > #endif /* LINUX_PCI_REGS_H */ > -- > 2.34.1 >
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 7d85c04fbba2..c1b243aec61c 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5034,6 +5034,20 @@ static u16 cxl_port_dvsec(struct pci_dev *dev) PCI_DVSEC_CXL_PORT); } +bool pcie_is_cxl_port(struct pci_dev *dev) +{ + if (!pcie_is_cxl(dev)) + return false; + + if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && + (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) && + (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)) + return false; + + return cxl_port_dvsec(dev); +} +EXPORT_SYMBOL_GPL(pcie_is_cxl_port); + static bool cxl_sbr_masked(struct pci_dev *dev) { u16 dvsec, reg; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 4f68414c3086..9324eb345f11 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1631,6 +1631,14 @@ static void set_pcie_thunderbolt(struct pci_dev *dev) dev->is_thunderbolt = 1; } +static void set_pcie_cxl(struct pci_dev *dev) +{ + u16 dvsec = pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, + PCI_DVSEC_CXL_FLEXBUS); + if (dvsec) + dev->is_cxl = 1; +} + static void set_pcie_untrusted(struct pci_dev *dev) { struct pci_dev *parent; @@ -1945,6 +1953,8 @@ int pci_setup_device(struct pci_dev *dev) /* Need to have dev->cfg_size ready */ set_pcie_thunderbolt(dev); + set_pcie_cxl(dev); + set_pcie_untrusted(dev); /* "Unknown power state" */ diff --git a/include/linux/pci.h b/include/linux/pci.h index 106ac83e3a7b..d3b1af9fb273 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -443,6 +443,7 @@ struct pci_dev { unsigned int is_hotplug_bridge:1; unsigned int shpc_managed:1; /* SHPC owned by shpchp */ unsigned int is_thunderbolt:1; /* Thunderbolt controller */ + unsigned int is_cxl:1; /* CXL alternate protocol */ /* * Devices marked being untrusted are the ones that can potentially * execute DMA attacks and similar. They are typically connected @@ -743,6 +744,9 @@ static inline bool pci_is_vga(struct pci_dev *pdev) return false; } +#define pcie_is_cxl(dev) (dev->is_cxl) +bool pcie_is_cxl_port(struct pci_dev *dev); + #define for_each_pci_bridge(dev, bus) \ list_for_each_entry(dev, &bus->devices, bus_list) \ if (!pci_is_bridge(dev)) {} else diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 12323b3334a9..5df6c74963c5 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1186,9 +1186,10 @@ #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000 #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000 -/* Compute Express Link (CXL r3.1, sec 8.1.5) */ +/* Compute Express Link (CXL r3.1, sec 8.1) */ #define PCI_DVSEC_CXL_PORT 3 #define PCI_DVSEC_CXL_PORT_CTL 0x0c #define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 +#define PCI_DVSEC_CXL_FLEXBUS 7 #endif /* LINUX_PCI_REGS_H */
CXL and AER drivers need the ability to identify CXL devices and CXL port devices. First, add set_pcie_cxl() with logic checking for CXL Flexbus DVSEC presence. The CXL Flexbus DVSEC presence is used because it is required for all the CXL PCIe devices.[1] Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL Flexbus presence. Add pcie_is_cxl() as a macro to return 'struct pci_dev::is_cxl', Add pcie_is_cxl_port() to check if a device is a CXL root port, CXL upstream switch port, or CXL downstream switch port. Also, verify the CXL extensions DVSEC for port is present.[1] [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended Capability (DVSEC) ID Assignment, Table 8-2 Signed-off-by: Terry Bowman <terry.bowman@amd.com> --- drivers/pci/pci.c | 14 ++++++++++++++ drivers/pci/probe.c | 10 ++++++++++ include/linux/pci.h | 4 ++++ include/uapi/linux/pci_regs.h | 3 ++- 4 files changed, 30 insertions(+), 1 deletion(-)