| Message ID | 20241031155646.15165-4-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Sanitize MBUS joining | expand |
On Thu, 31 Oct 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > We'll be wanting reprogram the PIPE_MBUS_DBOX_CTL registers wanting *to* reprogram I would've wanted to see conversion to struct intel_display here too, or at least a mention we're keeping it this way for backports, or something. A patch on top changing everything in one go is fine too. Reviewed-by: Jani Nikula <jani.nikula@intel.com> > during an upcoming MBUS sanitation stage. Extract the reprogramming > loop into a helper that doesn't depend on the full atomic state > so that it can be reused. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/skl_watermark.c | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c > index 7a7caaf7e87d..8a31508f94bb 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark.c > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c > @@ -3319,11 +3319,20 @@ static u32 pipe_mbus_dbox_ctl(const struct intel_crtc *crtc, > return val; > } > > +static void pipe_mbus_dbox_ctl_update(struct drm_i915_private *i915, > + const struct intel_dbuf_state *dbuf_state) > +{ > + struct intel_crtc *crtc; > + > + for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, dbuf_state->active_pipes) > + intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), > + pipe_mbus_dbox_ctl(crtc, dbuf_state)); > +} > + > static void intel_mbus_dbox_update(struct intel_atomic_state *state) > { > struct drm_i915_private *i915 = to_i915(state->base.dev); > const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state; > - const struct intel_crtc *crtc; > > if (DISPLAY_VER(i915) < 11) > return; > @@ -3335,9 +3344,7 @@ static void intel_mbus_dbox_update(struct intel_atomic_state *state) > new_dbuf_state->active_pipes == old_dbuf_state->active_pipes)) > return; > > - for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) > - intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), > - pipe_mbus_dbox_ctl(crtc, new_dbuf_state)); > + pipe_mbus_dbox_ctl_update(i915, new_dbuf_state); > } > > int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
On Fri, Nov 01, 2024 at 12:29:03PM +0200, Jani Nikula wrote: > On Thu, 31 Oct 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > We'll be wanting reprogram the PIPE_MBUS_DBOX_CTL registers > > wanting *to* reprogram > > I would've wanted to see conversion to struct intel_display here too, or > at least a mention we're keeping it this way for backports, or > something. A patch on top changing everything in one go is fine too. Yeah, IIRC I did it with intel_display originally but changed it in case we need to backport this. I can toss in a note stating as much. I think I tried to do a full conversion of skl_watermark.c at some point but at the time there were still so many depedencies left that it looked rather pointless. I can have another look at it now that we've progressed a bit further. > > Reviewed-by: Jani Nikula <jani.nikula@intel.com> Ta. > > > during an upcoming MBUS sanitation stage. Extract the reprogramming > > loop into a helper that doesn't depend on the full atomic state > > so that it can be reused. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > drivers/gpu/drm/i915/display/skl_watermark.c | 15 +++++++++++---- > > 1 file changed, 11 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c > > index 7a7caaf7e87d..8a31508f94bb 100644 > > --- a/drivers/gpu/drm/i915/display/skl_watermark.c > > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c > > @@ -3319,11 +3319,20 @@ static u32 pipe_mbus_dbox_ctl(const struct intel_crtc *crtc, > > return val; > > } > > > > +static void pipe_mbus_dbox_ctl_update(struct drm_i915_private *i915, > > + const struct intel_dbuf_state *dbuf_state) > > +{ > > + struct intel_crtc *crtc; > > + > > + for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, dbuf_state->active_pipes) > > + intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), > > + pipe_mbus_dbox_ctl(crtc, dbuf_state)); > > +} > > + > > static void intel_mbus_dbox_update(struct intel_atomic_state *state) > > { > > struct drm_i915_private *i915 = to_i915(state->base.dev); > > const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state; > > - const struct intel_crtc *crtc; > > > > if (DISPLAY_VER(i915) < 11) > > return; > > @@ -3335,9 +3344,7 @@ static void intel_mbus_dbox_update(struct intel_atomic_state *state) > > new_dbuf_state->active_pipes == old_dbuf_state->active_pipes)) > > return; > > > > - for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) > > - intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), > > - pipe_mbus_dbox_ctl(crtc, new_dbuf_state)); > > + pipe_mbus_dbox_ctl_update(i915, new_dbuf_state); > > } > > > > int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, > > -- > Jani Nikula, Intel
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 7a7caaf7e87d..8a31508f94bb 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3319,11 +3319,20 @@ static u32 pipe_mbus_dbox_ctl(const struct intel_crtc *crtc, return val; } +static void pipe_mbus_dbox_ctl_update(struct drm_i915_private *i915, + const struct intel_dbuf_state *dbuf_state) +{ + struct intel_crtc *crtc; + + for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, dbuf_state->active_pipes) + intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), + pipe_mbus_dbox_ctl(crtc, dbuf_state)); +} + static void intel_mbus_dbox_update(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state; - const struct intel_crtc *crtc; if (DISPLAY_VER(i915) < 11) return; @@ -3335,9 +3344,7 @@ static void intel_mbus_dbox_update(struct intel_atomic_state *state) new_dbuf_state->active_pipes == old_dbuf_state->active_pipes)) return; - for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) - intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), - pipe_mbus_dbox_ctl(crtc, new_dbuf_state)); + pipe_mbus_dbox_ctl_update(i915, new_dbuf_state); } int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,