| Message ID | 20241029091729.3317512-5-jamin_lin@aspeedtech.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Support RTC for AST2700 | expand |
On 10/29/24 10:17, Jamin Lin wrote: > Fix coding style issues from checkpatch.pl > > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Thanks, C. > --- > hw/sd/sdhci.c | 64 +++++++++++++++++++++++++++++++++------------------ > 1 file changed, 42 insertions(+), 22 deletions(-) > > diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c > index ed01499391..db7d547156 100644 > --- a/hw/sd/sdhci.c > +++ b/hw/sd/sdhci.c > @@ -234,7 +234,7 @@ static void sdhci_raise_insertion_irq(void *opaque) > > if (s->norintsts & SDHC_NIS_REMOVE) { > timer_mod(s->insert_timer, > - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); > + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); > } else { > s->prnsts = 0x1ff0000; > if (s->norintstsen & SDHC_NISEN_INSERT) { > @@ -252,7 +252,7 @@ static void sdhci_set_inserted(DeviceState *dev, bool level) > if ((s->norintsts & SDHC_NIS_REMOVE) && level) { > /* Give target some time to notice card ejection */ > timer_mod(s->insert_timer, > - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); > + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); > } else { > if (level) { > s->prnsts = 0x1ff0000; > @@ -290,9 +290,11 @@ static void sdhci_reset(SDHCIState *s) > timer_del(s->insert_timer); > timer_del(s->transfer_timer); > > - /* Set all registers to 0. Capabilities/Version registers are not cleared > + /* > + * Set all registers to 0. Capabilities/Version registers are not cleared > * and assumed to always preserve their value, given to them during > - * initialization */ > + * initialization > + */ > memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); > > /* Reset other state based on current card insertion/readonly status */ > @@ -306,7 +308,8 @@ static void sdhci_reset(SDHCIState *s) > > static void sdhci_poweron_reset(DeviceState *dev) > { > - /* QOM (ie power-on) reset. This is identical to reset > + /* > + * QOM (ie power-on) reset. This is identical to reset > * commanded via device register apart from handling of the > * 'pending insert on powerup' quirk. > */ > @@ -446,8 +449,10 @@ static void sdhci_read_block_from_card(SDHCIState *s) > s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; > } > > - /* If stop at block gap request was set and it's not the last block of > - * data - generate Block Event interrupt */ > + /* > + * If stop at block gap request was set and it's not the last block of > + * data - generate Block Event interrupt > + */ > if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && > s->blkcnt != 1) { > s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; > @@ -549,8 +554,10 @@ static void sdhci_write_block_to_card(SDHCIState *s) > sdhci_update_irq(s); > } > > -/* Write @size bytes of @value data to host controller @s Buffer Data Port > - * register */ > +/* > + * Write @size bytes of @value data to host controller @s Buffer Data Port > + * register > + */ > static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) > { > unsigned i; > @@ -595,9 +602,11 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) > return; > } > > - /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for > + /* > + * XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for > * possible stop at page boundary if initial address is not page aligned, > - * allow them to work properly */ > + * allow them to work properly > + */ > if ((s->sdmasysad % boundary_chk) == 0) { > page_aligned = true; > } > @@ -703,7 +712,8 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr) > dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2), > MEMTXATTRS_UNSPECIFIED); > adma2 = le64_to_cpu(adma2); > - /* The spec does not specify endianness of descriptor table. > + /* > + * The spec does not specify endianness of descriptor table. > * We currently assume that it is LE. > */ > dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; > @@ -978,8 +988,10 @@ static bool sdhci_can_issue_command(SDHCIState *s) > return true; > } > > -/* The Buffer Data Port register must be accessed in sequential and > - * continuous manner */ > +/* > + * The Buffer Data Port register must be accessed in sequential and > + * continuous manner > + */ > static inline bool > sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) > { > @@ -1207,8 +1219,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) > MASKED_WRITE(s->argument, mask, value); > break; > case SDHC_TRNMOD: > - /* DMA can be enabled only if it is supported as indicated by > - * capabilities register */ > + /* > + * DMA can be enabled only if it is supported as indicated by > + * capabilities register > + */ > if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { > value &= ~SDHC_TRNS_DMA; > } > @@ -1280,8 +1294,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) > } else { > s->norintsts &= ~SDHC_NIS_ERR; > } > - /* Quirk for Raspberry Pi: pending card insert interrupt > - * appears when first enabled after power on */ > + /* > + * Quirk for Raspberry Pi: pending card insert interrupt > + * appears when first enabled after power on > + */ > if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { > assert(s->pending_insert_quirk); > s->norintsts |= SDHC_NIS_INSERT; > @@ -1397,8 +1413,10 @@ void sdhci_initfn(SDHCIState *s) > { > qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); > > - s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); > - s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); > + s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, > + sdhci_raise_insertion_irq, s); > + s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, > + sdhci_data_transfer, s); > > s->io_ops = &sdhci_mmio_le_ops; > } > @@ -1446,11 +1464,13 @@ void sdhci_common_realize(SDHCIState *s, Error **errp) > > void sdhci_common_unrealize(SDHCIState *s) > { > - /* This function is expected to be called only once for each class: > + /* > + * This function is expected to be called only once for each class: > * - SysBus: via DeviceClass->unrealize(), > * - PCI: via PCIDeviceClass->exit(). > * However to avoid double-free and/or use-after-free we still nullify > - * this variable (better safe than sorry!). */ > + * this variable (better safe than sorry!). > + */ > g_free(s->fifo_buffer); > s->fifo_buffer = NULL; > }
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index ed01499391..db7d547156 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -234,7 +234,7 @@ static void sdhci_raise_insertion_irq(void *opaque) if (s->norintsts & SDHC_NIS_REMOVE) { timer_mod(s->insert_timer, - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); } else { s->prnsts = 0x1ff0000; if (s->norintstsen & SDHC_NISEN_INSERT) { @@ -252,7 +252,7 @@ static void sdhci_set_inserted(DeviceState *dev, bool level) if ((s->norintsts & SDHC_NIS_REMOVE) && level) { /* Give target some time to notice card ejection */ timer_mod(s->insert_timer, - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); } else { if (level) { s->prnsts = 0x1ff0000; @@ -290,9 +290,11 @@ static void sdhci_reset(SDHCIState *s) timer_del(s->insert_timer); timer_del(s->transfer_timer); - /* Set all registers to 0. Capabilities/Version registers are not cleared + /* + * Set all registers to 0. Capabilities/Version registers are not cleared * and assumed to always preserve their value, given to them during - * initialization */ + * initialization + */ memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); /* Reset other state based on current card insertion/readonly status */ @@ -306,7 +308,8 @@ static void sdhci_reset(SDHCIState *s) static void sdhci_poweron_reset(DeviceState *dev) { - /* QOM (ie power-on) reset. This is identical to reset + /* + * QOM (ie power-on) reset. This is identical to reset * commanded via device register apart from handling of the * 'pending insert on powerup' quirk. */ @@ -446,8 +449,10 @@ static void sdhci_read_block_from_card(SDHCIState *s) s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; } - /* If stop at block gap request was set and it's not the last block of - * data - generate Block Event interrupt */ + /* + * If stop at block gap request was set and it's not the last block of + * data - generate Block Event interrupt + */ if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt != 1) { s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; @@ -549,8 +554,10 @@ static void sdhci_write_block_to_card(SDHCIState *s) sdhci_update_irq(s); } -/* Write @size bytes of @value data to host controller @s Buffer Data Port - * register */ +/* + * Write @size bytes of @value data to host controller @s Buffer Data Port + * register + */ static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) { unsigned i; @@ -595,9 +602,11 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) return; } - /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for + /* + * XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for * possible stop at page boundary if initial address is not page aligned, - * allow them to work properly */ + * allow them to work properly + */ if ((s->sdmasysad % boundary_chk) == 0) { page_aligned = true; } @@ -703,7 +712,8 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr) dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2), MEMTXATTRS_UNSPECIFIED); adma2 = le64_to_cpu(adma2); - /* The spec does not specify endianness of descriptor table. + /* + * The spec does not specify endianness of descriptor table. * We currently assume that it is LE. */ dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; @@ -978,8 +988,10 @@ static bool sdhci_can_issue_command(SDHCIState *s) return true; } -/* The Buffer Data Port register must be accessed in sequential and - * continuous manner */ +/* + * The Buffer Data Port register must be accessed in sequential and + * continuous manner + */ static inline bool sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) { @@ -1207,8 +1219,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) MASKED_WRITE(s->argument, mask, value); break; case SDHC_TRNMOD: - /* DMA can be enabled only if it is supported as indicated by - * capabilities register */ + /* + * DMA can be enabled only if it is supported as indicated by + * capabilities register + */ if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { value &= ~SDHC_TRNS_DMA; } @@ -1280,8 +1294,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) } else { s->norintsts &= ~SDHC_NIS_ERR; } - /* Quirk for Raspberry Pi: pending card insert interrupt - * appears when first enabled after power on */ + /* + * Quirk for Raspberry Pi: pending card insert interrupt + * appears when first enabled after power on + */ if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { assert(s->pending_insert_quirk); s->norintsts |= SDHC_NIS_INSERT; @@ -1397,8 +1413,10 @@ void sdhci_initfn(SDHCIState *s) { qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); - s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); - s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); + s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, + sdhci_raise_insertion_irq, s); + s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, + sdhci_data_transfer, s); s->io_ops = &sdhci_mmio_le_ops; } @@ -1446,11 +1464,13 @@ void sdhci_common_realize(SDHCIState *s, Error **errp) void sdhci_common_unrealize(SDHCIState *s) { - /* This function is expected to be called only once for each class: + /* + * This function is expected to be called only once for each class: * - SysBus: via DeviceClass->unrealize(), * - PCI: via PCIDeviceClass->exit(). * However to avoid double-free and/or use-after-free we still nullify - * this variable (better safe than sorry!). */ + * this variable (better safe than sorry!). + */ g_free(s->fifo_buffer); s->fifo_buffer = NULL; }
Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- hw/sd/sdhci.c | 64 +++++++++++++++++++++++++++++++++------------------ 1 file changed, 42 insertions(+), 22 deletions(-)