| Message ID | 20240930092631.2997543-4-zhenzhong.duan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | intel_iommu: Enable stage-1 translation for emulated device | expand |
LGTM, thanks for the update Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com> > Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. > > > Add an new element scalable_mode in IntelIOMMUState to mark scalable > modern mode, this element will be exposed as an intel_iommu property > finally. > > For now, it's only a placehholder and used for address width > compatibility check and block host device passthrough until nesting > is supported. > > Signed-off-by: Yi Liu <yi.l.liu@intel.com> > Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> > Acked-by: Jason Wang <jasowang@redhat.com> > --- > include/hw/i386/intel_iommu.h | 1 + > hw/i386/intel_iommu.c | 23 ++++++++++++++++++----- > 2 files changed, 19 insertions(+), 5 deletions(-) > > diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h > index 1eb05c29fc..788ed42477 100644 > --- a/include/hw/i386/intel_iommu.h > +++ b/include/hw/i386/intel_iommu.h > @@ -262,6 +262,7 @@ struct IntelIOMMUState { > > bool caching_mode; /* RO - is cap CM enabled? */ > bool scalable_mode; /* RO - is Scalable Mode supported? */ > + bool scalable_modern; /* RO - is modern SM supported? */ > bool snoop_control; /* RO - is SNP filed supported? */ > > dma_addr_t root; /* Current root table pointer */ > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index be7c8a670b..9e6ef0cb99 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -3872,7 +3872,13 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIOMMUDevice *hiod, > return false; > } > > - return true; > + if (!s->scalable_modern) { > + /* All checks requested by VTD non-modern mode pass */ > + return true; > + } > + > + error_setg(errp, "host device is unsupported in scalable modern mode yet"); > + return false; > } > > static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, > @@ -4257,14 +4263,21 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) > } > } > > - /* Currently only address widths supported are 39 and 48 bits */ > - if ((s->aw_bits != VTD_HOST_AW_39BIT) && > - (s->aw_bits != VTD_HOST_AW_48BIT)) { > - error_setg(errp, "Supported values for aw-bits are: %d, %d", > + if (!s->scalable_modern && s->aw_bits != VTD_HOST_AW_39BIT && > + s->aw_bits != VTD_HOST_AW_48BIT) { > + error_setg(errp, "%s mode: supported values for aw-bits are: %d, %d", > + s->scalable_mode ? "Scalable" : "Legacy", > VTD_HOST_AW_39BIT, VTD_HOST_AW_48BIT); > return false; > } > > + if (s->scalable_modern && s->aw_bits != VTD_HOST_AW_48BIT) { > + error_setg(errp, > + "Scalable modern mode: supported values for aw-bits is: %d", > + VTD_HOST_AW_48BIT); > + return false; > + } > + > if (s->scalable_mode && !s->dma_drain) { > error_setg(errp, "Need to set dma_drain for scalable mode"); > return false; > -- > 2.34.1 > > >
On 2024/9/30 17:26, Zhenzhong Duan wrote: > Add an new element scalable_mode in IntelIOMMUState to mark scalable > modern mode, this element will be exposed as an intel_iommu property > finally. > > For now, it's only a placehholder and used for address width > compatibility check and block host device passthrough until nesting > is supported. > > Signed-off-by: Yi Liu <yi.l.liu@intel.com> > Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> > Acked-by: Jason Wang <jasowang@redhat.com> > --- > include/hw/i386/intel_iommu.h | 1 + > hw/i386/intel_iommu.c | 23 ++++++++++++++++++----- > 2 files changed, 19 insertions(+), 5 deletions(-) Reviewed-by: Yi Liu <yi.l.liu@intel.com> > diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h > index 1eb05c29fc..788ed42477 100644 > --- a/include/hw/i386/intel_iommu.h > +++ b/include/hw/i386/intel_iommu.h > @@ -262,6 +262,7 @@ struct IntelIOMMUState { > > bool caching_mode; /* RO - is cap CM enabled? */ > bool scalable_mode; /* RO - is Scalable Mode supported? */ > + bool scalable_modern; /* RO - is modern SM supported? */ > bool snoop_control; /* RO - is SNP filed supported? */ > > dma_addr_t root; /* Current root table pointer */ > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index be7c8a670b..9e6ef0cb99 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -3872,7 +3872,13 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIOMMUDevice *hiod, > return false; > } > > - return true; > + if (!s->scalable_modern) { > + /* All checks requested by VTD non-modern mode pass */ > + return true; > + } > + > + error_setg(errp, "host device is unsupported in scalable modern mode yet"); > + return false; > } > > static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, > @@ -4257,14 +4263,21 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) > } > } > > - /* Currently only address widths supported are 39 and 48 bits */ > - if ((s->aw_bits != VTD_HOST_AW_39BIT) && > - (s->aw_bits != VTD_HOST_AW_48BIT)) { > - error_setg(errp, "Supported values for aw-bits are: %d, %d", > + if (!s->scalable_modern && s->aw_bits != VTD_HOST_AW_39BIT && > + s->aw_bits != VTD_HOST_AW_48BIT) { > + error_setg(errp, "%s mode: supported values for aw-bits are: %d, %d", > + s->scalable_mode ? "Scalable" : "Legacy", > VTD_HOST_AW_39BIT, VTD_HOST_AW_48BIT); > return false; > } > > + if (s->scalable_modern && s->aw_bits != VTD_HOST_AW_48BIT) { > + error_setg(errp, > + "Scalable modern mode: supported values for aw-bits is: %d", > + VTD_HOST_AW_48BIT); > + return false; > + } > + > if (s->scalable_mode && !s->dma_drain) { > error_setg(errp, "Need to set dma_drain for scalable mode"); > return false;
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 1eb05c29fc..788ed42477 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -262,6 +262,7 @@ struct IntelIOMMUState { bool caching_mode; /* RO - is cap CM enabled? */ bool scalable_mode; /* RO - is Scalable Mode supported? */ + bool scalable_modern; /* RO - is modern SM supported? */ bool snoop_control; /* RO - is SNP filed supported? */ dma_addr_t root; /* Current root table pointer */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index be7c8a670b..9e6ef0cb99 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3872,7 +3872,13 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIOMMUDevice *hiod, return false; } - return true; + if (!s->scalable_modern) { + /* All checks requested by VTD non-modern mode pass */ + return true; + } + + error_setg(errp, "host device is unsupported in scalable modern mode yet"); + return false; } static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, @@ -4257,14 +4263,21 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) } } - /* Currently only address widths supported are 39 and 48 bits */ - if ((s->aw_bits != VTD_HOST_AW_39BIT) && - (s->aw_bits != VTD_HOST_AW_48BIT)) { - error_setg(errp, "Supported values for aw-bits are: %d, %d", + if (!s->scalable_modern && s->aw_bits != VTD_HOST_AW_39BIT && + s->aw_bits != VTD_HOST_AW_48BIT) { + error_setg(errp, "%s mode: supported values for aw-bits are: %d, %d", + s->scalable_mode ? "Scalable" : "Legacy", VTD_HOST_AW_39BIT, VTD_HOST_AW_48BIT); return false; } + if (s->scalable_modern && s->aw_bits != VTD_HOST_AW_48BIT) { + error_setg(errp, + "Scalable modern mode: supported values for aw-bits is: %d", + VTD_HOST_AW_48BIT); + return false; + } + if (s->scalable_mode && !s->dma_drain) { error_setg(errp, "Need to set dma_drain for scalable mode"); return false;