| Message ID | 20241101-sm8750-audio-v1-1-730aec176459@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: qcom: sm8750: Initial audio support (not yet complete) | expand |
On 11/1/2024 10:19 AM, Krzysztof Kozlowski wrote: > Add nodes for IPCC mailbox, SMP2P for ADSP, AOSS and the ADSP remoteproc > PAS loader (compatible with SM8550). > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8750.dtsi | 140 +++++++++++++++++++++++++++++++++++ > 1 file changed, 140 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi > index 98ab82caa007ee63c395a3ce0f517e2bbeb0aecb..eb826b154dcb2d8165426ba2225548efd7547da8 100644 > --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi [...] > > @@ -538,6 +566,17 @@ gcc: clock-controller@100000 { > #power-domain-cells = <1>; > }; > > + ipcc: mailbox@406000 { > + compatible = "qcom,sm8750-ipcc", "qcom,ipcc"; > + reg = <0 0x00406000 0 0x1000>; nit: unsure, but should thse be 0x0? > + > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <3>; > + > + #mbox-cells = <2>; > + }; > + > gpi_dma2: dma-controller@800000 { > compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma"; > reg = <0x0 0x00800000 0x0 0x60000>; > @@ -1975,6 +2014,19 @@ pdc: interrupt-controller@b220000 { > interrupt-controller; > }; > > + aoss_qmp: power-management@c300000 { > + compatible = "qcom,sm8750-aoss-qmp", "qcom,aoss-qmp"; > + reg = <0 0x0c300000 0 0x400>; Same as above. > + > + interrupt-parent = <&ipcc>; > + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP > + IRQ_TYPE_EDGE_RISING>; > + > + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; > + > + #clock-cells = <0>; > + }; > + > spmi_bus: spmi@c400000 { > compatible = "qcom,spmi-pmic-arb"; > reg = <0x0 0xc400000 0x0 0x3000>, > @@ -2884,6 +2936,94 @@ gem_noc: interconnect@24100000 { > #interconnect-cells = <2>; > }; > > + remoteproc_adsp: remoteproc@30000000 { > + compatible = "qcom,sm8750-adsp-pas", "qcom,sm8550-adsp-pas"; > + reg = <0 0x30000000 0 0x100>; Same as above. > + > + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; [...] Otherwise, LGTM. Reviewed-by: Melody Olvera <quic_molvera@quicinc.com> Thanks, Melody
On 01/11/2024 19:14, Melody Olvera wrote: > > > On 11/1/2024 10:19 AM, Krzysztof Kozlowski wrote: >> Add nodes for IPCC mailbox, SMP2P for ADSP, AOSS and the ADSP remoteproc >> PAS loader (compatible with SM8550). >> >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/sm8750.dtsi | 140 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 140 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> index 98ab82caa007ee63c395a3ce0f517e2bbeb0aecb..eb826b154dcb2d8165426ba2225548efd7547da8 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi > [...] >> >> @@ -538,6 +566,17 @@ gcc: clock-controller@100000 { >> #power-domain-cells = <1>; >> }; >> >> + ipcc: mailbox@406000 { >> + compatible = "qcom,sm8750-ipcc", "qcom,ipcc"; >> + reg = <0 0x00406000 0 0x1000>; > > nit: unsure, but should thse be 0x0? No, all recent upstream DTSI files nodes use simplified 0, because it is shorter. Maybe except few cases, but then these could be corrected instead. Best regards, Krzysztof
On Mon, Nov 04, 2024 at 09:36:46AM +0100, Krzysztof Kozlowski wrote: > On 01/11/2024 19:14, Melody Olvera wrote: > > > > > > On 11/1/2024 10:19 AM, Krzysztof Kozlowski wrote: > >> Add nodes for IPCC mailbox, SMP2P for ADSP, AOSS and the ADSP remoteproc > >> PAS loader (compatible with SM8550). > >> > >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > >> --- > >> arch/arm64/boot/dts/qcom/sm8750.dtsi | 140 +++++++++++++++++++++++++++++++++++ > >> 1 file changed, 140 insertions(+) > >> > >> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi > >> index 98ab82caa007ee63c395a3ce0f517e2bbeb0aecb..eb826b154dcb2d8165426ba2225548efd7547da8 100644 > >> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi > >> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi > > [...] > >> > >> @@ -538,6 +566,17 @@ gcc: clock-controller@100000 { > >> #power-domain-cells = <1>; > >> }; > >> > >> + ipcc: mailbox@406000 { > >> + compatible = "qcom,sm8750-ipcc", "qcom,ipcc"; > >> + reg = <0 0x00406000 0 0x1000>; > > > > nit: unsure, but should thse be 0x0? > > No, all recent upstream DTSI files nodes use simplified 0, because it is > shorter. Maybe except few cases, but then these could be corrected instead. I think most of the files (including x1e80100.dtsi) use a mixture of 0x0 and 0 here. I have been told several times to use 0x0 all the time.
On 04/11/2024 11:52, Dmitry Baryshkov wrote: > On Mon, Nov 04, 2024 at 09:36:46AM +0100, Krzysztof Kozlowski wrote: >> On 01/11/2024 19:14, Melody Olvera wrote: >>> >>> >>> On 11/1/2024 10:19 AM, Krzysztof Kozlowski wrote: >>>> Add nodes for IPCC mailbox, SMP2P for ADSP, AOSS and the ADSP remoteproc >>>> PAS loader (compatible with SM8550). >>>> >>>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >>>> --- >>>> arch/arm64/boot/dts/qcom/sm8750.dtsi | 140 +++++++++++++++++++++++++++++++++++ >>>> 1 file changed, 140 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi >>>> index 98ab82caa007ee63c395a3ce0f517e2bbeb0aecb..eb826b154dcb2d8165426ba2225548efd7547da8 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi >>> [...] >>>> >>>> @@ -538,6 +566,17 @@ gcc: clock-controller@100000 { >>>> #power-domain-cells = <1>; >>>> }; >>>> >>>> + ipcc: mailbox@406000 { >>>> + compatible = "qcom,sm8750-ipcc", "qcom,ipcc"; >>>> + reg = <0 0x00406000 0 0x1000>; >>> >>> nit: unsure, but should thse be 0x0? >> >> No, all recent upstream DTSI files nodes use simplified 0, because it is >> shorter. Maybe except few cases, but then these could be corrected instead. > > I think most of the files (including x1e80100.dtsi) use a mixture of 0x0 Most recent files upstreamed by Linaro use 0, not 0x0. git grep 'reg = <0' -- arch/arm64/boot/dts/qcom/sm8[56]50.dtsi | wc -l 384 git grep 'reg = <0x0' -- arch/arm64/boot/dts/qcom/sm8[56]50.dtsi | wc -l 30 git grep 'reg = <0' -- arch/arm64/boot/dts/qcom/x1e80100.dtsi | wc -l 234 git grep 'reg = <0x0' -- arch/arm64/boot/dts/qcom/x1e80100.dtsi | wc -l 65 And SM8750 builds on top of SM8650. > and 0 here. I have been told several times to use 0x0 all the time. I can't believe we have now long thread discussing this on this silly patch, but sure, do you have reference to Konrad's or Bjorn's preference? If want to be sure that before we start renaming everything to one style, we actually agree on style. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 98ab82caa007ee63c395a3ce0f517e2bbeb0aecb..eb826b154dcb2d8165426ba2225548efd7547da8 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -10,8 +10,10 @@ #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / { @@ -510,6 +512,32 @@ llcc_lpi_mem: llcc-lpi@ff800000 { }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <443>, <429>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; @@ -538,6 +566,17 @@ gcc: clock-controller@100000 { #power-domain-cells = <1>; }; + ipcc: mailbox@406000 { + compatible = "qcom,sm8750-ipcc", "qcom,ipcc"; + reg = <0 0x00406000 0 0x1000>; + + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + gpi_dma2: dma-controller@800000 { compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0x0 0x00800000 0x0 0x60000>; @@ -1975,6 +2014,19 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + aoss_qmp: power-management@c300000 { + compatible = "qcom,sm8750-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + spmi_bus: spmi@c400000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0 0xc400000 0x0 0x3000>, @@ -2884,6 +2936,94 @@ gem_noc: interconnect@24100000 { #interconnect-cells = <2>; }; + remoteproc_adsp: remoteproc@30000000 { + compatible = "qcom,sm8750-adsp-pas", "qcom,sm8550-adsp-pas"; + reg = <0 0x30000000 0 0x100>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid = <2>; + label = "lpass"; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = <GPR_DOMAIN_ID_ADSP>; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = <GPR_APM_MODULE_IID>; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1001 0x80>, + <&apps_smmu 0x1041 0x20>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = <GPR_PRM_MODULE_IID>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; + }; + }; + nsp_noc: interconnect@320c0000 { compatible = "qcom,sm8750-nsp-noc"; reg = <0x0 0x320c0000 0x0 0x13080>;
Add nodes for IPCC mailbox, SMP2P for ADSP, AOSS and the ADSP remoteproc PAS loader (compatible with SM8550). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 140 +++++++++++++++++++++++++++++++++++ 1 file changed, 140 insertions(+)