| Message ID | 20241026123058.28258-2-quic_rlaggysh@quicinc.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere, archived |
| Headers | show |
| Series | Add EPSS L3 provider support on SA8775P SoC | expand |
On Sat, Oct 26, 2024 at 12:30:56PM +0000, Raviteja Laggyshetty wrote: > Add Epoch Subsystem (EPSS) L3 interconnect provider binding on > SA8775P SoCs. > > Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> > --- > .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml > index 21dae0b92819..042ca44c32ec 100644 > --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml > +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml > @@ -34,6 +34,10 @@ properties: > - qcom,sm8250-epss-l3 > - qcom,sm8350-epss-l3 > - const: qcom,epss-l3 > + - items: > + - enum: > + - qcom,sa8775p-epss-l3 > + - const: qcom,epss-l3-perf Why is it -perf? What's so different about it? > > reg: > maxItems: 1 > -- > 2.39.2 >
On 10/26/2024 8:15 PM, Dmitry Baryshkov wrote: > On Sat, Oct 26, 2024 at 12:30:56PM +0000, Raviteja Laggyshetty wrote: >> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on >> SA8775P SoCs. >> >> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> >> --- >> .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >> index 21dae0b92819..042ca44c32ec 100644 >> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >> @@ -34,6 +34,10 @@ properties: >> - qcom,sm8250-epss-l3 >> - qcom,sm8350-epss-l3 >> - const: qcom,epss-l3 >> + - items: >> + - enum: >> + - qcom,sa8775p-epss-l3 >> + - const: qcom,epss-l3-perf > > Why is it -perf? What's so different about it? The EPSS instance in SA8775P uses PERF_STATE register instead of REG_L3_VOTE to scale L3 clocks. So adding new generic compatible "qcom,epss-l3-perf" for PERF_STATE register based l3 scaling. > >> >> reg: >> maxItems: 1 >> -- >> 2.39.2 >> >
On Wed, Oct 30, 2024 at 12:23:57PM +0530, Raviteja Laggyshetty wrote: > > > On 10/26/2024 8:15 PM, Dmitry Baryshkov wrote: > > On Sat, Oct 26, 2024 at 12:30:56PM +0000, Raviteja Laggyshetty wrote: > >> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on > >> SA8775P SoCs. > >> > >> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> > >> --- > >> .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 4 ++++ > >> 1 file changed, 4 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml > >> index 21dae0b92819..042ca44c32ec 100644 > >> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml > >> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml > >> @@ -34,6 +34,10 @@ properties: > >> - qcom,sm8250-epss-l3 > >> - qcom,sm8350-epss-l3 > >> - const: qcom,epss-l3 > >> + - items: > >> + - enum: > >> + - qcom,sa8775p-epss-l3 > >> + - const: qcom,epss-l3-perf > > > > Why is it -perf? What's so different about it? > > The EPSS instance in SA8775P uses PERF_STATE register instead of REG_L3_VOTE to scale L3 clocks. > So adding new generic compatible "qcom,epss-l3-perf" for PERF_STATE register based l3 scaling. Neither sm8250 nor sc7280 use this compatible, while they also use PERF_STATE register. > > > > > >> > >> reg: > >> maxItems: 1 > >> -- > >> 2.39.2 > >> > > >
On 11/1/2024 12:26 AM, Dmitry Baryshkov wrote: > On Wed, Oct 30, 2024 at 12:23:57PM +0530, Raviteja Laggyshetty wrote: >> >> >> On 10/26/2024 8:15 PM, Dmitry Baryshkov wrote: >>> On Sat, Oct 26, 2024 at 12:30:56PM +0000, Raviteja Laggyshetty wrote: >>>> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on >>>> SA8775P SoCs. >>>> >>>> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> >>>> --- >>>> .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 4 ++++ >>>> 1 file changed, 4 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>>> index 21dae0b92819..042ca44c32ec 100644 >>>> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>>> @@ -34,6 +34,10 @@ properties: >>>> - qcom,sm8250-epss-l3 >>>> - qcom,sm8350-epss-l3 >>>> - const: qcom,epss-l3 >>>> + - items: >>>> + - enum: >>>> + - qcom,sa8775p-epss-l3 >>>> + - const: qcom,epss-l3-perf >>> >>> Why is it -perf? What's so different about it? >> >> The EPSS instance in SA8775P uses PERF_STATE register instead of REG_L3_VOTE to scale L3 clocks. >> So adding new generic compatible "qcom,epss-l3-perf" for PERF_STATE register based l3 scaling. > > Neither sm8250 nor sc7280 use this compatible, while they also use > PERF_STATE register. > That is correct, both sm8250 and sc7280 use perf state register. The intention for adding "qcom,epss-l3-perf" generic compatible is to use it for the chipsets which use perf state register for l3 scaling. Using generic compatible avoids the need for adding chipset specific compatible in match table. >> >> >>> >>>> >>>> reg: >>>> maxItems: 1 >>>> -- >>>> 2.39.2 >>>> >>> >> >
On 4.11.2024 7:40 AM, Raviteja Laggyshetty wrote: > > > On 11/1/2024 12:26 AM, Dmitry Baryshkov wrote: >> On Wed, Oct 30, 2024 at 12:23:57PM +0530, Raviteja Laggyshetty wrote: >>> >>> >>> On 10/26/2024 8:15 PM, Dmitry Baryshkov wrote: >>>> On Sat, Oct 26, 2024 at 12:30:56PM +0000, Raviteja Laggyshetty wrote: >>>>> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on >>>>> SA8775P SoCs. >>>>> >>>>> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> >>>>> --- >>>>> .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 4 ++++ >>>>> 1 file changed, 4 insertions(+) >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>>>> index 21dae0b92819..042ca44c32ec 100644 >>>>> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>>>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>>>> @@ -34,6 +34,10 @@ properties: >>>>> - qcom,sm8250-epss-l3 >>>>> - qcom,sm8350-epss-l3 >>>>> - const: qcom,epss-l3 >>>>> + - items: >>>>> + - enum: >>>>> + - qcom,sa8775p-epss-l3 >>>>> + - const: qcom,epss-l3-perf >>>> >>>> Why is it -perf? What's so different about it? >>> >>> The EPSS instance in SA8775P uses PERF_STATE register instead of REG_L3_VOTE to scale L3 clocks. >>> So adding new generic compatible "qcom,epss-l3-perf" for PERF_STATE register based l3 scaling. >> >> Neither sm8250 nor sc7280 use this compatible, while they also use >> PERF_STATE register. >> > That is correct, both sm8250 and sc7280 use perf state register. > The intention for adding "qcom,epss-l3-perf" generic compatible is to use it for the chipsets which use perf state register for l3 scaling. > Using generic compatible avoids the need for adding chipset specific compatible in match table. That is exactly what bindings guidelines forbid. You need a SoC-specific compatible so that you can address platform- specific quirks that may arise in the future while keeping backwards compatibility with older device trees Konrad
On Mon, 4 Nov 2024 at 09:35, Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> wrote: > > On 4.11.2024 7:40 AM, Raviteja Laggyshetty wrote: > > > > > > On 11/1/2024 12:26 AM, Dmitry Baryshkov wrote: > >> On Wed, Oct 30, 2024 at 12:23:57PM +0530, Raviteja Laggyshetty wrote: > >>> > >>> > >>> On 10/26/2024 8:15 PM, Dmitry Baryshkov wrote: > >>>> On Sat, Oct 26, 2024 at 12:30:56PM +0000, Raviteja Laggyshetty wrote: > >>>>> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on > >>>>> SA8775P SoCs. > >>>>> > >>>>> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> > >>>>> --- > >>>>> .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 4 ++++ > >>>>> 1 file changed, 4 insertions(+) > >>>>> > >>>>> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml > >>>>> index 21dae0b92819..042ca44c32ec 100644 > >>>>> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml > >>>>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml > >>>>> @@ -34,6 +34,10 @@ properties: > >>>>> - qcom,sm8250-epss-l3 > >>>>> - qcom,sm8350-epss-l3 > >>>>> - const: qcom,epss-l3 > >>>>> + - items: > >>>>> + - enum: > >>>>> + - qcom,sa8775p-epss-l3 > >>>>> + - const: qcom,epss-l3-perf > >>>> > >>>> Why is it -perf? What's so different about it? > >>> > >>> The EPSS instance in SA8775P uses PERF_STATE register instead of REG_L3_VOTE to scale L3 clocks. > >>> So adding new generic compatible "qcom,epss-l3-perf" for PERF_STATE register based l3 scaling. > >> > >> Neither sm8250 nor sc7280 use this compatible, while they also use > >> PERF_STATE register. > >> > > That is correct, both sm8250 and sc7280 use perf state register. > > The intention for adding "qcom,epss-l3-perf" generic compatible is to use it for the chipsets which use perf state register for l3 scaling. > > Using generic compatible avoids the need for adding chipset specific compatible in match table. > > That is exactly what bindings guidelines forbid. > > You need a SoC-specific compatible so that you can address platform- > specific quirks that may arise in the future while keeping backwards > compatibility with older device trees The proposed bindings have SoC-specific compat. If that's not against the current rules, I'd prefer to have qcom,epss-l3-perf to be added to sc7280 and sm8250 too.
On 11/4/2024 3:05 PM, Konrad Dybcio wrote: > On 4.11.2024 7:40 AM, Raviteja Laggyshetty wrote: >> >> >> On 11/1/2024 12:26 AM, Dmitry Baryshkov wrote: >>> On Wed, Oct 30, 2024 at 12:23:57PM +0530, Raviteja Laggyshetty wrote: >>>> >>>> >>>> On 10/26/2024 8:15 PM, Dmitry Baryshkov wrote: >>>>> On Sat, Oct 26, 2024 at 12:30:56PM +0000, Raviteja Laggyshetty wrote: >>>>>> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on >>>>>> SA8775P SoCs. >>>>>> >>>>>> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> >>>>>> --- >>>>>> .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 4 ++++ >>>>>> 1 file changed, 4 insertions(+) >>>>>> >>>>>> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>>>>> index 21dae0b92819..042ca44c32ec 100644 >>>>>> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>>>>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>>>>> @@ -34,6 +34,10 @@ properties: >>>>>> - qcom,sm8250-epss-l3 >>>>>> - qcom,sm8350-epss-l3 >>>>>> - const: qcom,epss-l3 >>>>>> + - items: >>>>>> + - enum: >>>>>> + - qcom,sa8775p-epss-l3 >>>>>> + - const: qcom,epss-l3-perf >>>>> >>>>> Why is it -perf? What's so different about it? >>>> >>>> The EPSS instance in SA8775P uses PERF_STATE register instead of REG_L3_VOTE to scale L3 clocks. >>>> So adding new generic compatible "qcom,epss-l3-perf" for PERF_STATE register based l3 scaling. >>> >>> Neither sm8250 nor sc7280 use this compatible, while they also use >>> PERF_STATE register. >>> >> That is correct, both sm8250 and sc7280 use perf state register. >> The intention for adding "qcom,epss-l3-perf" generic compatible is to use it for the chipsets which use perf state register for l3 scaling. >> Using generic compatible avoids the need for adding chipset specific compatible in match table. > > That is exactly what bindings guidelines forbid. > > You need a SoC-specific compatible so that you can address platform- > specific quirks that may arise in the future while keeping backwards > compatibility with older device trees > > Konrad Got it, I will add both SoC-Specific and generic compatibles in the driver match table in next patch revision.
On 11/4/2024 4:08 PM, Dmitry Baryshkov wrote: > On Mon, 4 Nov 2024 at 09:35, Konrad Dybcio > <konrad.dybcio@oss.qualcomm.com> wrote: >> >> On 4.11.2024 7:40 AM, Raviteja Laggyshetty wrote: >>> >>> >>> On 11/1/2024 12:26 AM, Dmitry Baryshkov wrote: >>>> On Wed, Oct 30, 2024 at 12:23:57PM +0530, Raviteja Laggyshetty wrote: >>>>> >>>>> >>>>> On 10/26/2024 8:15 PM, Dmitry Baryshkov wrote: >>>>>> On Sat, Oct 26, 2024 at 12:30:56PM +0000, Raviteja Laggyshetty wrote: >>>>>>> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on >>>>>>> SA8775P SoCs. >>>>>>> >>>>>>> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> >>>>>>> --- >>>>>>> .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 4 ++++ >>>>>>> 1 file changed, 4 insertions(+) >>>>>>> >>>>>>> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>>>>>> index 21dae0b92819..042ca44c32ec 100644 >>>>>>> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>>>>>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>>>>>> @@ -34,6 +34,10 @@ properties: >>>>>>> - qcom,sm8250-epss-l3 >>>>>>> - qcom,sm8350-epss-l3 >>>>>>> - const: qcom,epss-l3 >>>>>>> + - items: >>>>>>> + - enum: >>>>>>> + - qcom,sa8775p-epss-l3 >>>>>>> + - const: qcom,epss-l3-perf >>>>>> >>>>>> Why is it -perf? What's so different about it? >>>>> >>>>> The EPSS instance in SA8775P uses PERF_STATE register instead of REG_L3_VOTE to scale L3 clocks. >>>>> So adding new generic compatible "qcom,epss-l3-perf" for PERF_STATE register based l3 scaling. >>>> >>>> Neither sm8250 nor sc7280 use this compatible, while they also use >>>> PERF_STATE register. >>>> >>> That is correct, both sm8250 and sc7280 use perf state register. >>> The intention for adding "qcom,epss-l3-perf" generic compatible is to use it for the chipsets which use perf state register for l3 scaling. >>> Using generic compatible avoids the need for adding chipset specific compatible in match table. >> >> That is exactly what bindings guidelines forbid. >> >> You need a SoC-specific compatible so that you can address platform- >> specific quirks that may arise in the future while keeping backwards >> compatibility with older device trees > > The proposed bindings have SoC-specific compat. If that's not against > the current rules, I'd prefer to have qcom,epss-l3-perf to be added to > sc7280 and sm8250 too. > > Existing compatibles for sc7280 and sm8250 do not break the backward compatibility. I will take up the update of generic compatibles for these two SoCs as separate patch series.
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 21dae0b92819..042ca44c32ec 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -34,6 +34,10 @@ properties: - qcom,sm8250-epss-l3 - qcom,sm8350-epss-l3 - const: qcom,epss-l3 + - items: + - enum: + - qcom,sa8775p-epss-l3 + - const: qcom,epss-l3-perf reg: maxItems: 1
Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SA8775P SoCs. Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> --- .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 4 ++++ 1 file changed, 4 insertions(+)