| Message ID | 20241014-armv7-cacheinfo-v2-0-38ab76d2b7fa@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | ARM: implement cacheinfo support (for v7/v7m) | expand |
On Mon, Oct 14, 2024 at 04:55:19PM +0300, Dmitry Baryshkov wrote: > Follow the ARM64 platform and implement simple cache information driver. > As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is > limited to the ARMv7 / ARMv7M, providing simple fallback or just > returning -EOPNOTSUPP in case of older platforms. > > In theory we should be able to skip CLIDR reading and assume that Dcache > and Icache (or unified L1 cache) always exist if CTR is supported and > returns sensible value. However I think this better be handled by the > maintainers of corresponding platforms. > > Other than just providing information to the userspace, this patchset is > required in order to implement L2 cache driver (and in the end CPU > frequency scaling) on ARMv7-based Qualcomm devices. Sudeep, Ard, Arnd, Russell, I have been struggling to get reviews for this for several months. Is there a chance to hear anything? I'd really like to scratch this off my 'pending' list. > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > Changes in v2: > - Handle cores like ARM1176, which have cpu_architecture() == > CPU_ARCH_ARMv7 (because of VMSAv7 implementation), but no CLIDR > register (because they are ARMv6) (Arnd). > - Link to v1: https://lore.kernel.org/r/20231231-armv7-cacheinfo-v1-0-9e8d440b59d9@linaro.org
(cc Linus) On Mon, 4 Nov 2024 at 12:51, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > On Mon, Oct 14, 2024 at 04:55:19PM +0300, Dmitry Baryshkov wrote: > > Follow the ARM64 platform and implement simple cache information driver. > > As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is > > limited to the ARMv7 / ARMv7M, providing simple fallback or just > > returning -EOPNOTSUPP in case of older platforms. > > > > In theory we should be able to skip CLIDR reading and assume that Dcache > > and Icache (or unified L1 cache) always exist if CTR is supported and > > returns sensible value. However I think this better be handled by the > > maintainers of corresponding platforms. > > > > Other than just providing information to the userspace, this patchset is > > required in order to implement L2 cache driver (and in the end CPU > > frequency scaling) on ARMv7-based Qualcomm devices. > > Sudeep, Ard, Arnd, Russell, I have been struggling to get reviews for > this for several months. Is there a chance to hear anything? I'd really > like to scratch this off my 'pending' list. > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > --- > > Changes in v2: > > - Handle cores like ARM1176, which have cpu_architecture() == > > CPU_ARCH_ARMv7 (because of VMSAv7 implementation), but no CLIDR > > register (because they are ARMv6) (Arnd). > > - Link to v1: https://lore.kernel.org/r/20231231-armv7-cacheinfo-v1-0-9e8d440b59d9@linaro.org > > -- > With best wishes > Dmitry
Hi Dmitry, On Mon, Oct 14, 2024 at 3:55 PM Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > Follow the ARM64 platform and implement simple cache information driver. > As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is > limited to the ARMv7 / ARMv7M, providing simple fallback or just > returning -EOPNOTSUPP in case of older platforms. > > In theory we should be able to skip CLIDR reading and assume that Dcache > and Icache (or unified L1 cache) always exist if CTR is supported and > returns sensible value. However I think this better be handled by the > maintainers of corresponding platforms. > > Other than just providing information to the userspace, this patchset is > required in order to implement L2 cache driver (and in the end CPU > frequency scaling) on ARMv7-based Qualcomm devices. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> I added my review tags to the v2 patches, can you put them into Russell's patch tracker? Yours, Linus Walleij
On Thu, Nov 07, 2024 at 02:55:55PM +0100, Linus Walleij wrote: > Hi Dmitry, > > On Mon, Oct 14, 2024 at 3:55 PM Dmitry Baryshkov > <dmitry.baryshkov@linaro.org> wrote: > > > Follow the ARM64 platform and implement simple cache information driver. > > As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is > > limited to the ARMv7 / ARMv7M, providing simple fallback or just > > returning -EOPNOTSUPP in case of older platforms. > > > > In theory we should be able to skip CLIDR reading and assume that Dcache > > and Icache (or unified L1 cache) always exist if CTR is supported and > > returns sensible value. However I think this better be handled by the > > maintainers of corresponding platforms. > > > > Other than just providing information to the userspace, this patchset is > > required in order to implement L2 cache driver (and in the end CPU > > frequency scaling) on ARMv7-based Qualcomm devices. > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > I added my review tags to the v2 patches, can you put them > into Russell's patch tracker? Done, 9432/1 and 9433/1, thank you!
Follow the ARM64 platform and implement simple cache information driver. As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is limited to the ARMv7 / ARMv7M, providing simple fallback or just returning -EOPNOTSUPP in case of older platforms. In theory we should be able to skip CLIDR reading and assume that Dcache and Icache (or unified L1 cache) always exist if CTR is supported and returns sensible value. However I think this better be handled by the maintainers of corresponding platforms. Other than just providing information to the userspace, this patchset is required in order to implement L2 cache driver (and in the end CPU frequency scaling) on ARMv7-based Qualcomm devices. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- Changes in v2: - Handle cores like ARM1176, which have cpu_architecture() == CPU_ARCH_ARMv7 (because of VMSAv7 implementation), but no CLIDR register (because they are ARMv6) (Arnd). - Link to v1: https://lore.kernel.org/r/20231231-armv7-cacheinfo-v1-0-9e8d440b59d9@linaro.org --- Dmitry Baryshkov (2): ARM: add CLIDR accessor functions ARM: implement cacheinfo support arch/arm/Kconfig | 1 + arch/arm/include/asm/cache.h | 6 ++ arch/arm/include/asm/cachetype.h | 13 +++ arch/arm/kernel/Makefile | 1 + arch/arm/kernel/cacheinfo.c | 173 +++++++++++++++++++++++++++++++++++++++ include/linux/cacheinfo.h | 2 +- 6 files changed, 195 insertions(+), 1 deletion(-) --- base-commit: 7f773fd61baa9b136faa5c4e6555aa64c758d07c change-id: 20231231-armv7-cacheinfo-9fa533ae371e Best regards,