diff mbox series

[04/13] dt-bindings: clock: eyeq: add Mobileye EyeQ6H central clocks

Message ID 20241031-mbly-clk-v1-4-89d8b28e3006@bootlin.com (mailing list archive)
State Superseded
Headers show
Series Usable clocks on Mobileye EyeQ5 & EyeQ6H | expand

Commit Message

Théo Lebrun Oct. 31, 2024, 3:52 p.m. UTC
Add clock indexes for EyeQ6H central OLB.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 include/dt-bindings/clock/mobileye,eyeq5-clk.h | 3 +++
 1 file changed, 3 insertions(+)

Comments

Krzysztof Kozlowski Nov. 1, 2024, 7:48 a.m. UTC | #1
On Thu, Oct 31, 2024 at 04:52:54PM +0100, Théo Lebrun wrote:
> Add clock indexes for EyeQ6H central OLB.
> 
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
>  include/dt-bindings/clock/mobileye,eyeq5-clk.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
> index 7d9e700b5e59573c45919865d9c68a9e8cf6a9eb..2356bc52646df9cfeb93df8120eb8f0bf80d97e9 100644
> --- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h
> +++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
> @@ -34,6 +34,9 @@
>  #define EQ6LC_PLL_PER		2
>  #define EQ6LC_PLL_VDI		3
>  
> +#define EQ6HC_CENTRAL_PLL_CPU	0
> +#define EQ6HC_CENTRAL_CPU_OCC	1
> +

Don't add define after define in separate patches. Logical change is to
add all defines at once, so multiple patches here should be squashed.

Best regards,
Krzysztof
Théo Lebrun Nov. 4, 2024, 4:16 p.m. UTC | #2
On Fri Nov 1, 2024 at 8:48 AM CET, Krzysztof Kozlowski wrote:
> On Thu, Oct 31, 2024 at 04:52:54PM +0100, Théo Lebrun wrote:
> > Add clock indexes for EyeQ6H central OLB.
> > 
> > Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> > ---
> >  include/dt-bindings/clock/mobileye,eyeq5-clk.h | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
> > index 7d9e700b5e59573c45919865d9c68a9e8cf6a9eb..2356bc52646df9cfeb93df8120eb8f0bf80d97e9 100644
> > --- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h
> > +++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
> > @@ -34,6 +34,9 @@
> >  #define EQ6LC_PLL_PER		2
> >  #define EQ6LC_PLL_VDI		3
> >  
> > +#define EQ6HC_CENTRAL_PLL_CPU	0
> > +#define EQ6HC_CENTRAL_CPU_OCC	1
> > +
>
> Don't add define after define in separate patches. Logical change is to
> add all defines at once, so multiple patches here should be squashed.

Sure, I was not sure so I leaned in the safe bet direction. Squashing is
much easier than splitting. Also improved the commit message, which
will look like this for next revision (incoming soon):

--

dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks

Add #defines for Mobileye clock controller:

 - EyeQ5 core 0 thru 3 clocks. Internally:

      EQ5C_PLL_CPU:           already exposed
      └── EQ5C_CPU_OCC:       unexposed, no reason to do so
          ├── EQ5C_CPU_CORE0: new!
          ├── EQ5C_CPU_CORE1: new!
          ├── EQ5C_CPU_CORE2: new!
          └── EQ5C_CPU_CORE3: new!

 - EyeQ5 peripheral clocks. Internally:

      EQ5C_PLL_PER:          already exposed
      └── EQ5C_PER_OCC:      new!
          └── EQ5C_PER_UART: new!

 - EyeQ6H central OLB. Internally:

      EQ6HC_CENTRAL_PLL_CPU:     new!
      └── EQ6HC_CENTRAL_CPU_OCC: new!

 - EyeQ6H west OLB. Internally:

      EQ6HC_WEST_PLL_PER:          new!
      └── EQ6HC_WEST_PER_OCC:      new!
          └── EQ6HC_WEST_PER_UART: new!

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>

--

Thanks Krzysztof,

--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
index 7d9e700b5e59573c45919865d9c68a9e8cf6a9eb..2356bc52646df9cfeb93df8120eb8f0bf80d97e9 100644
--- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h
+++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
@@ -34,6 +34,9 @@ 
 #define EQ6LC_PLL_PER		2
 #define EQ6LC_PLL_VDI		3
 
+#define EQ6HC_CENTRAL_PLL_CPU	0
+#define EQ6HC_CENTRAL_CPU_OCC	1
+
 #define EQ6HC_SOUTH_PLL_VDI		0
 #define EQ6HC_SOUTH_PLL_PCIE		1
 #define EQ6HC_SOUTH_PLL_PER		2