Message ID | 20241030-feature_poe_port_prio-v2-5-9559622ee47a@bootlin.com (mailing list archive) |
---|---|
State | Changes Requested |
Delegated to: | Netdev Maintainers |
Headers | show |
Series | Add support for PSE port priority | expand |
On Wed, Oct 30, 2024 at 05:53:07PM +0100, Kory Maincent wrote: ... > /** > * struct pse_control - a PSE control > @@ -440,18 +441,22 @@ int pse_controller_register(struct pse_controller_dev *pcdev) > > mutex_init(&pcdev->lock); > INIT_LIST_HEAD(&pcdev->pse_control_head); > + ret = ida_alloc_max(&pse_ida, INT_MAX, GFP_KERNEL); s/INT_MAX/U32_MAX ... > struct pse_control_status { > + u32 pse_id; > enum ethtool_podl_pse_admin_state podl_admin_state; ... > struct pse_controller_dev { > const struct pse_controller_ops *ops; > @@ -163,6 +166,7 @@ struct pse_controller_dev { > enum ethtool_pse_types types; > struct pse_pi *pi; > bool no_of_pse_pi; > + int id; u32 id It would be better to have one type for all variables.
On Thu, Oct 31, 2024 at 07:27:59AM +0100, Oleksij Rempel wrote: > On Wed, Oct 30, 2024 at 05:53:07PM +0100, Kory Maincent wrote: > > ... > > /** > > * struct pse_control - a PSE control > > @@ -440,18 +441,22 @@ int pse_controller_register(struct pse_controller_dev *pcdev) > > > > mutex_init(&pcdev->lock); > > INIT_LIST_HEAD(&pcdev->pse_control_head); > > + ret = ida_alloc_max(&pse_ida, INT_MAX, GFP_KERNEL); > > s/INT_MAX/U32_MAX * Return: The allocated ID, or %-ENOMEM if memory could not be allocated, * or %-ENOSPC if there are no free IDs. static inline int ida_alloc_max(struct ida *ida, unsigned int max, gfp_t gfp) We need to be careful here, at least theoretically. Assuming a 32 bit system, and you pass it U32_MAX, how does it return values in the range S32_MAX..U32_MAX when it also needs to be able to return negative numbers as errors? I think the correct value to pass is S32_MAX, because it will always fit in a u32, and there is space left for negative values for errors. But this is probably theoretical, no real system should have that many controllers. Andrew
On Thu, 31 Oct 2024 22:28:29 +0100 Andrew Lunn <andrew@lunn.ch> wrote: > On Thu, Oct 31, 2024 at 07:27:59AM +0100, Oleksij Rempel wrote: > > On Wed, Oct 30, 2024 at 05:53:07PM +0100, Kory Maincent wrote: > > > > ... > > > /** > > > * struct pse_control - a PSE control > > > @@ -440,18 +441,22 @@ int pse_controller_register(struct > > > pse_controller_dev *pcdev) > > > mutex_init(&pcdev->lock); > > > INIT_LIST_HEAD(&pcdev->pse_control_head); > > > + ret = ida_alloc_max(&pse_ida, INT_MAX, GFP_KERNEL); > > > > s/INT_MAX/U32_MAX > > * Return: The allocated ID, or %-ENOMEM if memory could not be allocated, > * or %-ENOSPC if there are no free IDs. > > static inline int ida_alloc_max(struct ida *ida, unsigned int max, gfp_t gfp) > > We need to be careful here, at least theoretically. Assuming a 32 bit > system, and you pass it U32_MAX, how does it return values in the > range S32_MAX..U32_MAX when it also needs to be able to return > negative numbers as errors? > > I think the correct value to pass is S32_MAX, because it will always > fit in a u32, and there is space left for negative values for errors. > > But this is probably theoretical, no real system should have that many > controllers. Indeed you are right we might have issue between S32_MAX and U32_MAX if we want to return errors. Small question, is S32_MAX better than INT_MAX? Is there a point to limit it to 32 bits? Regards,
diff --git a/drivers/net/pse-pd/pse_core.c b/drivers/net/pse-pd/pse_core.c index 2906ce173f66..68297428f6b5 100644 --- a/drivers/net/pse-pd/pse_core.c +++ b/drivers/net/pse-pd/pse_core.c @@ -13,6 +13,7 @@ static DEFINE_MUTEX(pse_list_mutex); static LIST_HEAD(pse_controller_list); +static DEFINE_IDA(pse_ida); /** * struct pse_control - a PSE control @@ -440,18 +441,22 @@ int pse_controller_register(struct pse_controller_dev *pcdev) mutex_init(&pcdev->lock); INIT_LIST_HEAD(&pcdev->pse_control_head); + ret = ida_alloc_max(&pse_ida, INT_MAX, GFP_KERNEL); + if (ret < 0) + return ret; + pcdev->id = ret; if (!pcdev->nr_lines) pcdev->nr_lines = 1; ret = of_load_pse_pis(pcdev); if (ret) - return ret; + goto free_pse_ida; if (pcdev->ops->setup_pi_matrix) { ret = pcdev->ops->setup_pi_matrix(pcdev); if (ret) - return ret; + goto free_pse_ida; } /* Each regulator name len is pcdev dev name + 7 char + @@ -468,15 +473,17 @@ int pse_controller_register(struct pse_controller_dev *pcdev) continue; reg_name = devm_kzalloc(pcdev->dev, reg_name_len, GFP_KERNEL); - if (!reg_name) - return -ENOMEM; + if (!reg_name) { + ret = -ENOMEM; + goto free_pse_ida; + } snprintf(reg_name, reg_name_len, "pse-%s_pi%d", dev_name(pcdev->dev), i); ret = devm_pse_pi_regulator_register(pcdev, reg_name, i); if (ret) - return ret; + goto free_pse_ida; } mutex_lock(&pse_list_mutex); @@ -484,6 +491,10 @@ int pse_controller_register(struct pse_controller_dev *pcdev) mutex_unlock(&pse_list_mutex); return 0; + +free_pse_ida: + ida_free(&pse_ida, pcdev->id); + return ret; } EXPORT_SYMBOL_GPL(pse_controller_register); @@ -494,6 +505,7 @@ EXPORT_SYMBOL_GPL(pse_controller_register); void pse_controller_unregister(struct pse_controller_dev *pcdev) { pse_release_pis(pcdev); + ida_free(&pse_ida, pcdev->id); mutex_lock(&pse_list_mutex); list_del(&pcdev->list); mutex_unlock(&pse_list_mutex); @@ -750,6 +762,7 @@ static int _pse_ethtool_get_status(struct pse_controller_dev *pcdev, return -EOPNOTSUPP; } + status->pse_id = pcdev->id; return ops->ethtool_get_status(pcdev, id, extack, status); } diff --git a/include/linux/pse-pd/pse.h b/include/linux/pse-pd/pse.h index 85a08c349256..5312488cb3cf 100644 --- a/include/linux/pse-pd/pse.h +++ b/include/linux/pse-pd/pse.h @@ -31,6 +31,7 @@ struct pse_control_config { /** * struct pse_control_status - PSE control/channel status. * + * @pse_id: index number of the PSE. Set by PSE core. * @podl_admin_state: operational state of the PoDL PSE * functions. IEEE 802.3-2018 30.15.1.1.2 aPoDLPSEAdminState * @podl_pw_status: power detection status of the PoDL PSE. @@ -52,6 +53,7 @@ struct pse_control_config { * ranges */ struct pse_control_status { + u32 pse_id; enum ethtool_podl_pse_admin_state podl_admin_state; enum ethtool_podl_pse_pw_d_status podl_pw_status; enum ethtool_c33_pse_admin_state c33_admin_state; @@ -150,6 +152,7 @@ struct pse_pi { * @types: types of the PSE controller * @pi: table of PSE PIs described in this controller device * @no_of_pse_pi: flag set if the pse_pis devicetree node is not used + * @id: Index of the PSE */ struct pse_controller_dev { const struct pse_controller_ops *ops; @@ -163,6 +166,7 @@ struct pse_controller_dev { enum ethtool_pse_types types; struct pse_pi *pi; bool no_of_pse_pi; + int id; }; #if IS_ENABLED(CONFIG_PSE_CONTROLLER)