mbox

[PULL,00/14] MIPS patches for 2024-11-04

Message ID 20241104105250.57818-1-philmd@linaro.org (mailing list archive)
State New
Headers show

Pull-request

https://github.com/philmd/qemu.git tags/mips-20241104

Message

Philippe Mathieu-Daudé Nov. 4, 2024, 10:52 a.m. UTC 
The following changes since commit 92ec7805190313c9e628f8fc4eb4f932c15247bd:

  Merge tag 'pull-riscv-to-apply-20241031-1' of https://github.com/alistair23/qemu into staging (2024-10-31 16:34:25 +0000)

are available in the Git repository at:

  https://github.com/philmd/qemu.git tags/mips-20241104

for you to fetch changes up to a144a3baa61e3fca1a7946685128c349dd92c76f:

  target/mips: Remove unused CPUMIPSState::current_fpu field (2024-11-03 05:52:49 -0300)

----------------------------------------------------------------
MIPS patches queue

- Migrate missing CP0 TLB MemoryMapID register (Yongbok)
- Enable MSA ASE for mips32r6-generic (Aleksandar)
- Convert Loongson LEXT opcodes to decodetree (Philippe)
- Introduce ase_3d_available and disas_mt_available helpers (Philippe)

----------------------------------------------------------------

Aleksandar Markovic (1):
  target/mips: Enable MSA ASE for mips32r6-generic

Philippe Mathieu-Daudé (12):
  target/mips: Extract decode_64bit_enabled() helper
  target/mips: Simplify Loongson MULTU.G opcode
  target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP
  target/mips: Convert Loongson DDIV.G opcodes to decodetree
  target/mips: Convert Loongson DIV.G opcodes to decodetree
  target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree
  target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree
  target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree
  target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext
  target/mips: Introduce ase_3d_available() helper
  target/mips: Introduce disas_mt_available()
  target/mips: Remove unused CPUMIPSState::current_fpu field

Yongbok Kim (1):
  target/mips: Migrate TLB MemoryMapID register

 target/mips/cpu.h                         |   7 +-
 target/mips/mips-defs.h                   |   2 -
 target/mips/tcg/translate.h               |   8 +
 target/mips/tcg/godson2.decode            |  27 ++
 target/mips/tcg/loong-ext.decode          |  28 ++
 target/mips/sysemu/machine.c              |   9 +-
 target/mips/tcg/loong_translate.c         | 271 ++++++++++++++
 target/mips/tcg/translate.c               | 415 +++++-----------------
 target/mips/cpu-defs.c.inc                |  16 +-
 target/mips/tcg/micromips_translate.c.inc |   5 +-
 target/mips/tcg/meson.build               |   3 +
 11 files changed, 452 insertions(+), 339 deletions(-)
 create mode 100644 target/mips/tcg/godson2.decode
 create mode 100644 target/mips/tcg/loong-ext.decode
 create mode 100644 target/mips/tcg/loong_translate.c

Comments

Peter Maydell Nov. 5, 2024, 3:47 p.m. UTC | #1 
On Mon, 4 Nov 2024 at 10:53, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> The following changes since commit 92ec7805190313c9e628f8fc4eb4f932c15247bd:
>
>   Merge tag 'pull-riscv-to-apply-20241031-1' of https://github.com/alistair23/qemu into staging (2024-10-31 16:34:25 +0000)
>
> are available in the Git repository at:
>
>   https://github.com/philmd/qemu.git tags/mips-20241104
>
> for you to fetch changes up to a144a3baa61e3fca1a7946685128c349dd92c76f:
>
>   target/mips: Remove unused CPUMIPSState::current_fpu field (2024-11-03 05:52:49 -0300)
>
> ----------------------------------------------------------------
> MIPS patches queue
>
> - Migrate missing CP0 TLB MemoryMapID register (Yongbok)
> - Enable MSA ASE for mips32r6-generic (Aleksandar)
> - Convert Loongson LEXT opcodes to decodetree (Philippe)
> - Introduce ase_3d_available and disas_mt_available helpers (Philippe)
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/9.2
for any user-visible changes.

-- PMM