| Message ID | 20241108-qcs615-mm-dt-nodes-v1-1-b2669cac0624@quicinc.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Add support for clock controllers and CPU scaling for QCS615 | expand |
On Fri, Nov 08, 2024 at 11:54:04AM +0530, Taniya Das wrote: > Add support for video, camera, display and gpu clock controller nodes > for QCS615 platform. > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 51 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > index 868808918fd2cdf3f23fcb43ead61b2abfc776f7..8c98ac77dc5c665ef296e65ac76c1b59be485abb 100644 > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > @@ -3,7 +3,11 @@ > * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. > */ > > +#include <dt-bindings/clock/qcom,qcs615-camcc.h> > +#include <dt-bindings/clock/qcom,qcs615-dispcc.h> > #include <dt-bindings/clock/qcom,qcs615-gcc.h> > +#include <dt-bindings/clock/qcom,qcs615-gpucc.h> > +#include <dt-bindings/clock/qcom,qcs615-videocc.h> > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/interconnect/qcom,icc.h> > #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> > @@ -488,6 +492,18 @@ qup_uart0_rx: qup-uart0-rx-state { > }; > }; > > + gpucc: clock-controller@5090000 { > + compatible = "qcom,qcs615-gpucc"; > + reg = <0 0x5090000 0 0x9000>; Please pad address field to 8 digits (just the address, not the size) > + > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GPLL0>; > + > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > dc_noc: interconnect@9160000 { > reg = <0x0 0x09160000 0x0 0x3200>; > compatible = "qcom,qcs615-dc-noc"; > @@ -502,6 +518,41 @@ gem_noc: interconnect@9680000 { > qcom,bcm-voters = <&apps_bcm_voter>; > }; > > + videocc: clock-controller@ab00000 { > + compatible = "qcom,qcs615-videocc"; > + reg = <0 0xab00000 0 0x10000>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&sleep_clk>; > + > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > + camcc: clock-controller@ad00000 { > + compatible = "qcom,qcs615-camcc"; > + reg = <0 0xad00000 0 0x10000>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > + dispcc: clock-controller@af00000 { > + compatible = "qcom,qcs615-dispcc"; > + reg = <0 0xaf00000 0 0x20000>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; > + > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > pdc: interrupt-controller@b220000 { > compatible = "qcom,qcs615-pdc", "qcom,pdc"; > reg = <0x0 0x0b220000 0x0 0x30000>, > > -- > 2.45.2 >
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index 868808918fd2cdf3f23fcb43ead61b2abfc776f7..8c98ac77dc5c665ef296e65ac76c1b59be485abb 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -3,7 +3,11 @@ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ +#include <dt-bindings/clock/qcom,qcs615-camcc.h> +#include <dt-bindings/clock/qcom,qcs615-dispcc.h> #include <dt-bindings/clock/qcom,qcs615-gcc.h> +#include <dt-bindings/clock/qcom,qcs615-gpucc.h> +#include <dt-bindings/clock/qcom,qcs615-videocc.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> @@ -488,6 +492,18 @@ qup_uart0_rx: qup-uart0-rx-state { }; }; + gpucc: clock-controller@5090000 { + compatible = "qcom,qcs615-gpucc"; + reg = <0 0x5090000 0 0x9000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + dc_noc: interconnect@9160000 { reg = <0x0 0x09160000 0x0 0x3200>; compatible = "qcom,qcs615-dc-noc"; @@ -502,6 +518,41 @@ gem_noc: interconnect@9680000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + videocc: clock-controller@ab00000 { + compatible = "qcom,qcs615-videocc"; + reg = <0 0xab00000 0 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,qcs615-camcc"; + reg = <0 0xad00000 0 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,qcs615-dispcc"; + reg = <0 0xaf00000 0 0x20000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,qcs615-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>,
Add support for video, camera, display and gpu clock controller nodes for QCS615 platform. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)