diff mbox series

[v5,1/2] perf arm-spe: Prepare for adding data source packet implementations for other cores

Message ID 20241108202946.16835-2-ilkka@os.amperecomputing.com (mailing list archive)
State New
Headers show
Series perf arm-spe: Add support for SPE Data Source packet on AmpereOne | expand

Commit Message

Ilkka Koskinen Nov. 8, 2024, 8:29 p.m. UTC 
Split Data Source Packet handling to prepare adding support for
other implementations.

Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>
---
 tools/perf/util/arm-spe.c | 42 ++++++++++++++++++++++++++++-----------
 1 file changed, 30 insertions(+), 12 deletions(-)

Comments

Leo Yan Nov. 11, 2024, 12:55 p.m. UTC | #1 
On Fri, Nov 08, 2024 at 08:29:45PM +0000, Ilkka Koskinen wrote:
> 
> Split Data Source Packet handling to prepare adding support for
> other implementations.
> 
> Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>

Reviewed-by: Leo Yan <leo.yan@arm.com>

> ---
>  tools/perf/util/arm-spe.c | 42 ++++++++++++++++++++++++++++-----------
>  1 file changed, 30 insertions(+), 12 deletions(-)
> 
> diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
> index dbf13f47879c..3064c3f22806 100644
> --- a/tools/perf/util/arm-spe.c
> +++ b/tools/perf/util/arm-spe.c
> @@ -103,6 +103,18 @@ struct arm_spe_queue {
>         u32                             flags;
>  };
> 
> +struct data_source_handle {
> +       const struct midr_range *midr_ranges;
> +       void (*ds_synth)(const struct arm_spe_record *record,
> +                        union perf_mem_data_src *data_src);
> +};
> +
> +#define DS(range, func)                                        \
> +       {                                               \
> +               .midr_ranges = range,                   \
> +               .ds_synth = arm_spe__synth_##func,      \
> +       }
> +
>  static void arm_spe_dump(struct arm_spe *spe __maybe_unused,
>                          unsigned char *buf, size_t len)
>  {
> @@ -532,6 +544,10 @@ static void arm_spe__synth_data_source_common(const struct arm_spe_record *recor
>         }
>  }
> 
> +static const struct data_source_handle data_source_handles[] = {
> +       DS(common_ds_encoding_cpus, data_source_common),
> +};
> +
>  static void arm_spe__synth_memory_level(const struct arm_spe_record *record,
>                                         union perf_mem_data_src *data_src)
>  {
> @@ -555,12 +571,14 @@ static void arm_spe__synth_memory_level(const struct arm_spe_record *record,
>                 data_src->mem_lvl |= PERF_MEM_LVL_REM_CCE1;
>  }
> 
> -static bool arm_spe__is_common_ds_encoding(struct arm_spe_queue *speq)
> +static bool arm_spe__synth_ds(struct arm_spe_queue *speq,
> +                             const struct arm_spe_record *record,
> +                             union perf_mem_data_src *data_src)
>  {
>         struct arm_spe *spe = speq->spe;
> -       bool is_in_cpu_list;
>         u64 *metadata = NULL;
> -       u64 midr = 0;
> +       u64 midr;
> +       unsigned int i;
> 
>         /* Metadata version 1 assumes all CPUs are the same (old behavior) */
>         if (spe->metadata_ver == 1) {
> @@ -592,18 +610,20 @@ static bool arm_spe__is_common_ds_encoding(struct arm_spe_queue *speq)
>                 midr = metadata[ARM_SPE_CPU_MIDR];
>         }
> 
> -       is_in_cpu_list = is_midr_in_range_list(midr, common_ds_encoding_cpus);
> -       if (is_in_cpu_list)
> -               return true;
> -       else
> -               return false;
> +       for (i = 0; i < ARRAY_SIZE(data_source_handles); i++) {
> +               if (is_midr_in_range_list(midr, data_source_handles[i].midr_ranges)) {
> +                       data_source_handles[i].ds_synth(record, data_src);
> +                       return true;
> +               }
> +       }
> +
> +       return false;
>  }
> 
>  static u64 arm_spe__synth_data_source(struct arm_spe_queue *speq,
>                                       const struct arm_spe_record *record)
>  {
>         union perf_mem_data_src data_src = { .mem_op = PERF_MEM_OP_NA };
> -       bool is_common = arm_spe__is_common_ds_encoding(speq);
> 
>         if (record->op & ARM_SPE_OP_LD)
>                 data_src.mem_op = PERF_MEM_OP_LOAD;
> @@ -612,9 +632,7 @@ static u64 arm_spe__synth_data_source(struct arm_spe_queue *speq,
>         else
>                 return 0;
> 
> -       if (is_common)
> -               arm_spe__synth_data_source_common(record, &data_src);
> -       else
> +       if (!arm_spe__synth_ds(speq, record, &data_src))
>                 arm_spe__synth_memory_level(record, &data_src);
> 
>         if (record->type & (ARM_SPE_TLB_ACCESS | ARM_SPE_TLB_MISS)) {
> --
> 2.47.0
> 
>
diff mbox series

Patch

diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
index dbf13f47879c..3064c3f22806 100644
--- a/tools/perf/util/arm-spe.c
+++ b/tools/perf/util/arm-spe.c
@@ -103,6 +103,18 @@  struct arm_spe_queue {
 	u32				flags;
 };
 
+struct data_source_handle {
+	const struct midr_range *midr_ranges;
+	void (*ds_synth)(const struct arm_spe_record *record,
+			 union perf_mem_data_src *data_src);
+};
+
+#define DS(range, func)					\
+	{						\
+		.midr_ranges = range,			\
+		.ds_synth = arm_spe__synth_##func,	\
+	}
+
 static void arm_spe_dump(struct arm_spe *spe __maybe_unused,
 			 unsigned char *buf, size_t len)
 {
@@ -532,6 +544,10 @@  static void arm_spe__synth_data_source_common(const struct arm_spe_record *recor
 	}
 }
 
+static const struct data_source_handle data_source_handles[] = {
+	DS(common_ds_encoding_cpus, data_source_common),
+};
+
 static void arm_spe__synth_memory_level(const struct arm_spe_record *record,
 					union perf_mem_data_src *data_src)
 {
@@ -555,12 +571,14 @@  static void arm_spe__synth_memory_level(const struct arm_spe_record *record,
 		data_src->mem_lvl |= PERF_MEM_LVL_REM_CCE1;
 }
 
-static bool arm_spe__is_common_ds_encoding(struct arm_spe_queue *speq)
+static bool arm_spe__synth_ds(struct arm_spe_queue *speq,
+			      const struct arm_spe_record *record,
+			      union perf_mem_data_src *data_src)
 {
 	struct arm_spe *spe = speq->spe;
-	bool is_in_cpu_list;
 	u64 *metadata = NULL;
-	u64 midr = 0;
+	u64 midr;
+	unsigned int i;
 
 	/* Metadata version 1 assumes all CPUs are the same (old behavior) */
 	if (spe->metadata_ver == 1) {
@@ -592,18 +610,20 @@  static bool arm_spe__is_common_ds_encoding(struct arm_spe_queue *speq)
 		midr = metadata[ARM_SPE_CPU_MIDR];
 	}
 
-	is_in_cpu_list = is_midr_in_range_list(midr, common_ds_encoding_cpus);
-	if (is_in_cpu_list)
-		return true;
-	else
-		return false;
+	for (i = 0; i < ARRAY_SIZE(data_source_handles); i++) {
+		if (is_midr_in_range_list(midr, data_source_handles[i].midr_ranges)) {
+			data_source_handles[i].ds_synth(record, data_src);
+			return true;
+		}
+	}
+
+	return false;
 }
 
 static u64 arm_spe__synth_data_source(struct arm_spe_queue *speq,
 				      const struct arm_spe_record *record)
 {
 	union perf_mem_data_src	data_src = { .mem_op = PERF_MEM_OP_NA };
-	bool is_common = arm_spe__is_common_ds_encoding(speq);
 
 	if (record->op & ARM_SPE_OP_LD)
 		data_src.mem_op = PERF_MEM_OP_LOAD;
@@ -612,9 +632,7 @@  static u64 arm_spe__synth_data_source(struct arm_spe_queue *speq,
 	else
 		return 0;
 
-	if (is_common)
-		arm_spe__synth_data_source_common(record, &data_src);
-	else
+	if (!arm_spe__synth_ds(speq, record, &data_src))
 		arm_spe__synth_memory_level(record, &data_src);
 
 	if (record->type & (ARM_SPE_TLB_ACCESS | ARM_SPE_TLB_MISS)) {