diff mbox series

[v2,4/4] media: platform: rzg2l-cru: Add support for RAW10/12/14 data

Message ID 20241112124614.646281-5-dan.scally@ideasonboard.com (mailing list archive)
State New
Headers show
Series Extend RAW format support for rzg2l-cru driver | expand

Commit Message

Dan Scally Nov. 12, 2024, 12:46 p.m. UTC 
From: Daniel Scally <dan.scally+renesas@ideasonboard.com>

Add support to the rzg2l-cru driver to capture 10/12/14 bit bayer
data and output it into the CRU's 64-bit packed pixel format.

Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Daniel Scally <dan.scally+renesas@ideasonboard.com>
---
Changes in v2:

	- Minor updates accounting for rebase

 .../platform/renesas/rzg2l-cru/rzg2l-csi2.c   | 12 +++
 .../platform/renesas/rzg2l-cru/rzg2l-ip.c     | 84 +++++++++++++++++++
 2 files changed, 96 insertions(+)

Comments

Jacopo Mondi Nov. 12, 2024, 1:52 p.m. UTC | #1 
Hi Dan

On Tue, Nov 12, 2024 at 12:46:14PM +0000, Daniel Scally wrote:
> From: Daniel Scally <dan.scally+renesas@ideasonboard.com>
>
> Add support to the rzg2l-cru driver to capture 10/12/14 bit bayer
> data and output it into the CRU's 64-bit packed pixel format.
>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Signed-off-by: Daniel Scally <dan.scally+renesas@ideasonboard.com>

Looks good to me
Reviewed-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>

Thanks
  j


> ---
> Changes in v2:
>
> 	- Minor updates accounting for rebase
>
>  .../platform/renesas/rzg2l-cru/rzg2l-csi2.c   | 12 +++
>  .../platform/renesas/rzg2l-cru/rzg2l-ip.c     | 84 +++++++++++++++++++
>  2 files changed, 96 insertions(+)
>
> diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
> index cbefd43de09b..e77cce2a8ddf 100644
> --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
> +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
> @@ -192,6 +192,18 @@ static const struct rzg2l_csi2_format rzg2l_csi2_formats[] = {
>  	{ .code = MEDIA_BUS_FMT_SGBRG8_1X8, .bpp = 8, },
>  	{ .code = MEDIA_BUS_FMT_SGRBG8_1X8, .bpp = 8, },
>  	{ .code = MEDIA_BUS_FMT_SRGGB8_1X8, .bpp = 8, },
> +	{ .code = MEDIA_BUS_FMT_SBGGR10_1X10, .bpp = 10, },
> +	{ .code = MEDIA_BUS_FMT_SGBRG10_1X10, .bpp = 10, },
> +	{ .code = MEDIA_BUS_FMT_SGRBG10_1X10, .bpp = 10, },
> +	{ .code = MEDIA_BUS_FMT_SRGGB10_1X10, .bpp = 10, },
> +	{ .code = MEDIA_BUS_FMT_SBGGR12_1X12, .bpp = 12, },
> +	{ .code = MEDIA_BUS_FMT_SGBRG12_1X12, .bpp = 12, },
> +	{ .code = MEDIA_BUS_FMT_SGRBG12_1X12, .bpp = 12, },
> +	{ .code = MEDIA_BUS_FMT_SRGGB12_1X12, .bpp = 12, },
> +	{ .code = MEDIA_BUS_FMT_SBGGR14_1X14, .bpp = 14, },
> +	{ .code = MEDIA_BUS_FMT_SGBRG14_1X14, .bpp = 14, },
> +	{ .code = MEDIA_BUS_FMT_SGRBG14_1X14, .bpp = 14, },
> +	{ .code = MEDIA_BUS_FMT_SRGGB14_1X14, .bpp = 14, },
>  };
>
>  static inline struct rzg2l_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
> diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c
> index 399a337dbafb..3e93c801f1b5 100644
> --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c
> +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c
> @@ -47,6 +47,90 @@ static const struct rzg2l_cru_ip_format rzg2l_cru_ip_formats[] = {
>  		.icndmr = 0,
>  		.yuv = false,
>  	},
> +	{
> +		.code = MEDIA_BUS_FMT_SBGGR10_1X10,
> +		.format = V4L2_PIX_FMT_CRU_SBGGR10,
> +		.datatype = MIPI_CSI2_DT_RAW10,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SGBRG10_1X10,
> +		.format = V4L2_PIX_FMT_CRU_SGBRG10,
> +		.datatype = MIPI_CSI2_DT_RAW10,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SGRBG10_1X10,
> +		.format = V4L2_PIX_FMT_CRU_SGRBG10,
> +		.datatype = MIPI_CSI2_DT_RAW10,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SRGGB10_1X10,
> +		.format = V4L2_PIX_FMT_CRU_SRGGB10,
> +		.datatype = MIPI_CSI2_DT_RAW10,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SBGGR12_1X12,
> +		.format = V4L2_PIX_FMT_CRU_SBGGR12,
> +		.datatype = MIPI_CSI2_DT_RAW12,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SGBRG12_1X12,
> +		.format = V4L2_PIX_FMT_CRU_SGBRG12,
> +		.datatype = MIPI_CSI2_DT_RAW12,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SGRBG12_1X12,
> +		.format = V4L2_PIX_FMT_CRU_SGRBG12,
> +		.datatype = MIPI_CSI2_DT_RAW12,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SRGGB12_1X12,
> +		.format = V4L2_PIX_FMT_CRU_SRGGB12,
> +		.datatype = MIPI_CSI2_DT_RAW12,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SBGGR14_1X14,
> +		.format = V4L2_PIX_FMT_CRU_SBGGR14,
> +		.datatype = MIPI_CSI2_DT_RAW14,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SGBRG14_1X14,
> +		.format = V4L2_PIX_FMT_CRU_SGBRG14,
> +		.datatype = MIPI_CSI2_DT_RAW14,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SGRBG14_1X14,
> +		.format = V4L2_PIX_FMT_CRU_SGRBG14,
> +		.datatype = MIPI_CSI2_DT_RAW14,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SRGGB14_1X14,
> +		.format = V4L2_PIX_FMT_CRU_SRGGB14,
> +		.datatype = MIPI_CSI2_DT_RAW14,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
>  };
>
>  const struct rzg2l_cru_ip_format *rzg2l_cru_ip_code_to_fmt(unsigned int code)
> --
> 2.34.1
>
Laurent Pinchart Nov. 12, 2024, 5:59 p.m. UTC | #2 
Hi Dan,

Thank you for the patch.

On Tue, Nov 12, 2024 at 12:46:14PM +0000, Daniel Scally wrote:
> From: Daniel Scally <dan.scally+renesas@ideasonboard.com>
> 
> Add support to the rzg2l-cru driver to capture 10/12/14 bit bayer
> data and output it into the CRU's 64-bit packed pixel format.
> 
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Signed-off-by: Daniel Scally <dan.scally+renesas@ideasonboard.com>

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> ---
> Changes in v2:
> 
> 	- Minor updates accounting for rebase
> 
>  .../platform/renesas/rzg2l-cru/rzg2l-csi2.c   | 12 +++
>  .../platform/renesas/rzg2l-cru/rzg2l-ip.c     | 84 +++++++++++++++++++
>  2 files changed, 96 insertions(+)
> 
> diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
> index cbefd43de09b..e77cce2a8ddf 100644
> --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
> +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
> @@ -192,6 +192,18 @@ static const struct rzg2l_csi2_format rzg2l_csi2_formats[] = {
>  	{ .code = MEDIA_BUS_FMT_SGBRG8_1X8, .bpp = 8, },
>  	{ .code = MEDIA_BUS_FMT_SGRBG8_1X8, .bpp = 8, },
>  	{ .code = MEDIA_BUS_FMT_SRGGB8_1X8, .bpp = 8, },
> +	{ .code = MEDIA_BUS_FMT_SBGGR10_1X10, .bpp = 10, },
> +	{ .code = MEDIA_BUS_FMT_SGBRG10_1X10, .bpp = 10, },
> +	{ .code = MEDIA_BUS_FMT_SGRBG10_1X10, .bpp = 10, },
> +	{ .code = MEDIA_BUS_FMT_SRGGB10_1X10, .bpp = 10, },
> +	{ .code = MEDIA_BUS_FMT_SBGGR12_1X12, .bpp = 12, },
> +	{ .code = MEDIA_BUS_FMT_SGBRG12_1X12, .bpp = 12, },
> +	{ .code = MEDIA_BUS_FMT_SGRBG12_1X12, .bpp = 12, },
> +	{ .code = MEDIA_BUS_FMT_SRGGB12_1X12, .bpp = 12, },
> +	{ .code = MEDIA_BUS_FMT_SBGGR14_1X14, .bpp = 14, },
> +	{ .code = MEDIA_BUS_FMT_SGBRG14_1X14, .bpp = 14, },
> +	{ .code = MEDIA_BUS_FMT_SGRBG14_1X14, .bpp = 14, },
> +	{ .code = MEDIA_BUS_FMT_SRGGB14_1X14, .bpp = 14, },
>  };
>  
>  static inline struct rzg2l_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
> diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c
> index 399a337dbafb..3e93c801f1b5 100644
> --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c
> +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c
> @@ -47,6 +47,90 @@ static const struct rzg2l_cru_ip_format rzg2l_cru_ip_formats[] = {
>  		.icndmr = 0,
>  		.yuv = false,
>  	},
> +	{
> +		.code = MEDIA_BUS_FMT_SBGGR10_1X10,
> +		.format = V4L2_PIX_FMT_CRU_SBGGR10,
> +		.datatype = MIPI_CSI2_DT_RAW10,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SGBRG10_1X10,
> +		.format = V4L2_PIX_FMT_CRU_SGBRG10,
> +		.datatype = MIPI_CSI2_DT_RAW10,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SGRBG10_1X10,
> +		.format = V4L2_PIX_FMT_CRU_SGRBG10,
> +		.datatype = MIPI_CSI2_DT_RAW10,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SRGGB10_1X10,
> +		.format = V4L2_PIX_FMT_CRU_SRGGB10,
> +		.datatype = MIPI_CSI2_DT_RAW10,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SBGGR12_1X12,
> +		.format = V4L2_PIX_FMT_CRU_SBGGR12,
> +		.datatype = MIPI_CSI2_DT_RAW12,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SGBRG12_1X12,
> +		.format = V4L2_PIX_FMT_CRU_SGBRG12,
> +		.datatype = MIPI_CSI2_DT_RAW12,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SGRBG12_1X12,
> +		.format = V4L2_PIX_FMT_CRU_SGRBG12,
> +		.datatype = MIPI_CSI2_DT_RAW12,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SRGGB12_1X12,
> +		.format = V4L2_PIX_FMT_CRU_SRGGB12,
> +		.datatype = MIPI_CSI2_DT_RAW12,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SBGGR14_1X14,
> +		.format = V4L2_PIX_FMT_CRU_SBGGR14,
> +		.datatype = MIPI_CSI2_DT_RAW14,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SGBRG14_1X14,
> +		.format = V4L2_PIX_FMT_CRU_SGBRG14,
> +		.datatype = MIPI_CSI2_DT_RAW14,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SGRBG14_1X14,
> +		.format = V4L2_PIX_FMT_CRU_SGRBG14,
> +		.datatype = MIPI_CSI2_DT_RAW14,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
> +	{
> +		.code = MEDIA_BUS_FMT_SRGGB14_1X14,
> +		.format = V4L2_PIX_FMT_CRU_SRGGB14,
> +		.datatype = MIPI_CSI2_DT_RAW14,
> +		.icndmr = 0,
> +		.yuv = false,
> +	},
>  };
>  
>  const struct rzg2l_cru_ip_format *rzg2l_cru_ip_code_to_fmt(unsigned int code)
>
diff mbox series

Patch

diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
index cbefd43de09b..e77cce2a8ddf 100644
--- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
+++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
@@ -192,6 +192,18 @@  static const struct rzg2l_csi2_format rzg2l_csi2_formats[] = {
 	{ .code = MEDIA_BUS_FMT_SGBRG8_1X8, .bpp = 8, },
 	{ .code = MEDIA_BUS_FMT_SGRBG8_1X8, .bpp = 8, },
 	{ .code = MEDIA_BUS_FMT_SRGGB8_1X8, .bpp = 8, },
+	{ .code = MEDIA_BUS_FMT_SBGGR10_1X10, .bpp = 10, },
+	{ .code = MEDIA_BUS_FMT_SGBRG10_1X10, .bpp = 10, },
+	{ .code = MEDIA_BUS_FMT_SGRBG10_1X10, .bpp = 10, },
+	{ .code = MEDIA_BUS_FMT_SRGGB10_1X10, .bpp = 10, },
+	{ .code = MEDIA_BUS_FMT_SBGGR12_1X12, .bpp = 12, },
+	{ .code = MEDIA_BUS_FMT_SGBRG12_1X12, .bpp = 12, },
+	{ .code = MEDIA_BUS_FMT_SGRBG12_1X12, .bpp = 12, },
+	{ .code = MEDIA_BUS_FMT_SRGGB12_1X12, .bpp = 12, },
+	{ .code = MEDIA_BUS_FMT_SBGGR14_1X14, .bpp = 14, },
+	{ .code = MEDIA_BUS_FMT_SGBRG14_1X14, .bpp = 14, },
+	{ .code = MEDIA_BUS_FMT_SGRBG14_1X14, .bpp = 14, },
+	{ .code = MEDIA_BUS_FMT_SRGGB14_1X14, .bpp = 14, },
 };
 
 static inline struct rzg2l_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c
index 399a337dbafb..3e93c801f1b5 100644
--- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c
+++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c
@@ -47,6 +47,90 @@  static const struct rzg2l_cru_ip_format rzg2l_cru_ip_formats[] = {
 		.icndmr = 0,
 		.yuv = false,
 	},
+	{
+		.code = MEDIA_BUS_FMT_SBGGR10_1X10,
+		.format = V4L2_PIX_FMT_CRU_SBGGR10,
+		.datatype = MIPI_CSI2_DT_RAW10,
+		.icndmr = 0,
+		.yuv = false,
+	},
+	{
+		.code = MEDIA_BUS_FMT_SGBRG10_1X10,
+		.format = V4L2_PIX_FMT_CRU_SGBRG10,
+		.datatype = MIPI_CSI2_DT_RAW10,
+		.icndmr = 0,
+		.yuv = false,
+	},
+	{
+		.code = MEDIA_BUS_FMT_SGRBG10_1X10,
+		.format = V4L2_PIX_FMT_CRU_SGRBG10,
+		.datatype = MIPI_CSI2_DT_RAW10,
+		.icndmr = 0,
+		.yuv = false,
+	},
+	{
+		.code = MEDIA_BUS_FMT_SRGGB10_1X10,
+		.format = V4L2_PIX_FMT_CRU_SRGGB10,
+		.datatype = MIPI_CSI2_DT_RAW10,
+		.icndmr = 0,
+		.yuv = false,
+	},
+	{
+		.code = MEDIA_BUS_FMT_SBGGR12_1X12,
+		.format = V4L2_PIX_FMT_CRU_SBGGR12,
+		.datatype = MIPI_CSI2_DT_RAW12,
+		.icndmr = 0,
+		.yuv = false,
+	},
+	{
+		.code = MEDIA_BUS_FMT_SGBRG12_1X12,
+		.format = V4L2_PIX_FMT_CRU_SGBRG12,
+		.datatype = MIPI_CSI2_DT_RAW12,
+		.icndmr = 0,
+		.yuv = false,
+	},
+	{
+		.code = MEDIA_BUS_FMT_SGRBG12_1X12,
+		.format = V4L2_PIX_FMT_CRU_SGRBG12,
+		.datatype = MIPI_CSI2_DT_RAW12,
+		.icndmr = 0,
+		.yuv = false,
+	},
+	{
+		.code = MEDIA_BUS_FMT_SRGGB12_1X12,
+		.format = V4L2_PIX_FMT_CRU_SRGGB12,
+		.datatype = MIPI_CSI2_DT_RAW12,
+		.icndmr = 0,
+		.yuv = false,
+	},
+	{
+		.code = MEDIA_BUS_FMT_SBGGR14_1X14,
+		.format = V4L2_PIX_FMT_CRU_SBGGR14,
+		.datatype = MIPI_CSI2_DT_RAW14,
+		.icndmr = 0,
+		.yuv = false,
+	},
+	{
+		.code = MEDIA_BUS_FMT_SGBRG14_1X14,
+		.format = V4L2_PIX_FMT_CRU_SGBRG14,
+		.datatype = MIPI_CSI2_DT_RAW14,
+		.icndmr = 0,
+		.yuv = false,
+	},
+	{
+		.code = MEDIA_BUS_FMT_SGRBG14_1X14,
+		.format = V4L2_PIX_FMT_CRU_SGRBG14,
+		.datatype = MIPI_CSI2_DT_RAW14,
+		.icndmr = 0,
+		.yuv = false,
+	},
+	{
+		.code = MEDIA_BUS_FMT_SRGGB14_1X14,
+		.format = V4L2_PIX_FMT_CRU_SRGGB14,
+		.datatype = MIPI_CSI2_DT_RAW14,
+		.icndmr = 0,
+		.yuv = false,
+	},
 };
 
 const struct rzg2l_cru_ip_format *rzg2l_cru_ip_code_to_fmt(unsigned int code)