| Message ID | 20241111214516.208820-1-marex@denx.de (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | clk: imx: pll14xx: Extend dynamic rates support to PLL1416x | expand |
On 11/12/2024, Marek Vasut wrote: > The pll1416x PLL so far only supports rates from a rate table passed > during initialization. Calculating PLL settings dynamically helps in > case e.g. multiple video outputs are used and they each need their own > separate source of accurate pixel clock on i.MX8MP. In that case, e.g. > PLL1416x PLL3 can be used as another Video PLL for another output. Just want to point out that i.MX8MP audio AXI clock is supposed to be derived from PLL3 to run at 600MHz in nominal mode(i.MX8MP data sheet specifies that rate). So, if a particular i.MX8MP system doesn't use audio, PLL3 can be a free clock source to be used by an i.MX8MP display pipeline, otherwise, video_pll1_out is supposed to be shared by i.MX8MP MIPI DSI and LVDS display pipelines. Currently, IMX8MP_CLK_AUDIO_AXI_SRC's parent is assigned to IMX8MP_SYS_PLL1_800M in imx8mp.dtsi. Although it's rate is assigned to 600MHz, the actual rate is 400MHz according to clk_summary because the divider cannot find a ratio to reach 600MHz from the clock source running at 800MHz. Looking at imx8mp_audio_axi_sels[], sys_pll3_out is the only free/appropriate clock source that can derive 600MHz audio AXI clock from. Maybe, someone will change IMX8MP_CLK_AUDIO_AXI_SRC's parent to IMX8MP_SYS_PLL3_OUT ? pgc_audio: power-domain@5 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, <&clk IMX8MP_CLK_AUDIO_AXI>; assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, <&clk IMX8MP_CLK_AUDIO_AXI_SRC>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_SYS_PLL1_800M>; assigned-clock-rates = <400000000>, <600000000>; }; sys_pll1_ref_sel 1 1 0 24000000 0 0 50000 Y deviceless no_connection_id sys_pll1 1 1 0 800000000 0 0 50000 Y deviceless no_connection_id sys_pll1_bypass 1 1 0 800000000 0 0 50000 Y deviceless no_connection_id sys_pll1_out 4 4 0 800000000 0 0 50000 Y deviceless no_connection_id sys_pll1_800m 6 6 0 800000000 0 0 50000 Y deviceless no_connection_id ... audio_axi 1 1 0 400000000 0 0 50000 Y power-domain@5 no_connection_id deviceless no_connection_id audio_axi_root 0 0 0 400000000 0 0 50000 Y deviceless no_connection_id
On 11/12/24 4:26 AM, Liu Ying wrote: > On 11/12/2024, Marek Vasut wrote: >> The pll1416x PLL so far only supports rates from a rate table passed >> during initialization. Calculating PLL settings dynamically helps in >> case e.g. multiple video outputs are used and they each need their own >> separate source of accurate pixel clock on i.MX8MP. In that case, e.g. >> PLL1416x PLL3 can be used as another Video PLL for another output. > > Just want to point out that i.MX8MP audio AXI clock is supposed to be > derived from PLL3 to run at 600MHz in nominal mode(i.MX8MP data sheet > specifies that rate). So, if a particular i.MX8MP system doesn't use > audio, PLL3 can be a free clock source to be used by an i.MX8MP display > pipeline, otherwise, video_pll1_out is supposed to be shared by i.MX8MP > MIPI DSI and LVDS display pipelines. In the end, I started using Audio PLL and Video PLL PLL1443x for accurate pixel clock generation and PLL3 to feed CLKOUTn where the less accurate PLL3 PLL1416x is just fine. With the disparate display requirements, sharing one Video PLL for multiple outputs like DSI and LVDS is unrealistic. (maybe the next SoC should have some nice PLL per display output) > Currently, IMX8MP_CLK_AUDIO_AXI_SRC's parent is assigned to > IMX8MP_SYS_PLL1_800M in imx8mp.dtsi. Although it's rate is assigned > to 600MHz, the actual rate is 400MHz according to clk_summary because > the divider cannot find a ratio to reach 600MHz from the clock source > running at 800MHz. Looking at imx8mp_audio_axi_sels[], sys_pll3_out > is the only free/appropriate clock source that can derive 600MHz audio > AXI clock from. Maybe, someone will change IMX8MP_CLK_AUDIO_AXI_SRC's > parent to IMX8MP_SYS_PLL3_OUT ? Is the 400 MHz sufficient for audio-axi or does it have some negative performance impact ? If the later, better send a patch to use PLL3 for audio-axi . Thanks !
On 11/13/2024, Marek Vasut wrote: > On 11/12/24 4:26 AM, Liu Ying wrote: >> On 11/12/2024, Marek Vasut wrote: >>> The pll1416x PLL so far only supports rates from a rate table passed >>> during initialization. Calculating PLL settings dynamically helps in >>> case e.g. multiple video outputs are used and they each need their own >>> separate source of accurate pixel clock on i.MX8MP. In that case, e.g. >>> PLL1416x PLL3 can be used as another Video PLL for another output. >> >> Just want to point out that i.MX8MP audio AXI clock is supposed to be >> derived from PLL3 to run at 600MHz in nominal mode(i.MX8MP data sheet >> specifies that rate). So, if a particular i.MX8MP system doesn't use >> audio, PLL3 can be a free clock source to be used by an i.MX8MP display >> pipeline, otherwise, video_pll1_out is supposed to be shared by i.MX8MP >> MIPI DSI and LVDS display pipelines. > > In the end, I started using Audio PLL and Video PLL PLL1443x for accurate pixel clock generation and PLL3 to feed CLKOUTn where the less accurate PLL3 PLL1416x is just fine. If audio PLLs or PLL3 are free, I think you may use them for video output. > > With the disparate display requirements, sharing one Video PLL for multiple outputs like DSI and LVDS is unrealistic. (maybe the next SoC should have some nice PLL per display output) I think there are 2 cases where we may or have to share one video PLL for DSI and LVDS. 1）It happens that the clock rate requirements of the 2 display pipelines can be met by one video PLL, e.g., an i.MX8MP platform uses both DSI to HDMI and LVDS to HDMI bridges - it's probably good enough to have users use typical display mode combinations, like 1920x1080p@60 (DSI) + 1280x720p@60(LVDS). In this case, we share one video PLL deliberately. 2) If audio PLLs and PLL3 are used already(very likely by audio subsystem), then the 2 display pipelines have to share one video PLL. It's possible that the video PLL cannot meet the clock rate requirements for one or both of them unfortunately, but maybe that's something we have to accept. > >> Currently, IMX8MP_CLK_AUDIO_AXI_SRC's parent is assigned to >> IMX8MP_SYS_PLL1_800M in imx8mp.dtsi. Although it's rate is assigned >> to 600MHz, the actual rate is 400MHz according to clk_summary because >> the divider cannot find a ratio to reach 600MHz from the clock source >> running at 800MHz. Looking at imx8mp_audio_axi_sels[], sys_pll3_out >> is the only free/appropriate clock source that can derive 600MHz audio >> AXI clock from. Maybe, someone will change IMX8MP_CLK_AUDIO_AXI_SRC's >> parent to IMX8MP_SYS_PLL3_OUT ? > Is the 400 MHz sufficient for audio-axi or does it have some negative performance impact ? If the later, better send a patch to use PLL3 for audio-axi . I'm adding Shengjiu to comment the audio part. > > Thanks !
Hi > > On 11/13/2024, Marek Vasut wrote: > > On 11/12/24 4:26 AM, Liu Ying wrote: > >> On 11/12/2024, Marek Vasut wrote: > >>> The pll1416x PLL so far only supports rates from a rate table passed > >>> during initialization. Calculating PLL settings dynamically helps in > >>> case e.g. multiple video outputs are used and they each need their > >>> own separate source of accurate pixel clock on i.MX8MP. In that case, e.g. > >>> PLL1416x PLL3 can be used as another Video PLL for another output. > >> > >> Just want to point out that i.MX8MP audio AXI clock is supposed to be > >> derived from PLL3 to run at 600MHz in nominal mode(i.MX8MP data sheet > >> specifies that rate). So, if a particular i.MX8MP system doesn't use > >> audio, PLL3 can be a free clock source to be used by an i.MX8MP > >> display pipeline, otherwise, video_pll1_out is supposed to be shared > >> by i.MX8MP MIPI DSI and LVDS display pipelines. > > > > In the end, I started using Audio PLL and Video PLL PLL1443x for accurate > pixel clock generation and PLL3 to feed CLKOUTn where the less accurate PLL3 > PLL1416x is just fine. > > If audio PLLs or PLL3 are free, I think you may use them for video output. > > > > > With the disparate display requirements, sharing one Video PLL for > > multiple outputs like DSI and LVDS is unrealistic. (maybe the next SoC > > should have some nice PLL per display output) > > I think there are 2 cases where we may or have to share one video PLL for DSI > and LVDS. > 1）It happens that the clock rate requirements of the 2 display pipelines > can be met by one video PLL, e.g., an i.MX8MP platform uses both > DSI to HDMI and LVDS to HDMI bridges - it's probably good enough to > have users use typical display mode combinations, like 1920x1080p@60 > (DSI) + 1280x720p@60(LVDS). > > In this case, we share one video PLL deliberately. > > > 2) If audio PLLs and PLL3 are used already(very likely by audio subsystem), > then the 2 display pipelines have to share one video PLL. > It's possible that the video PLL cannot meet the clock rate requirements > for one or both of them unfortunately, but maybe that's something we > have to accept. > > > > >> Currently, IMX8MP_CLK_AUDIO_AXI_SRC's parent is assigned to > >> IMX8MP_SYS_PLL1_800M in imx8mp.dtsi. Although it's rate is assigned > >> to 600MHz, the actual rate is 400MHz according to clk_summary because > >> the divider cannot find a ratio to reach 600MHz from the clock source > >> running at 800MHz. Looking at imx8mp_audio_axi_sels[], sys_pll3_out > >> is the only free/appropriate clock source that can derive 600MHz > >> audio AXI clock from. Maybe, someone will change > >> IMX8MP_CLK_AUDIO_AXI_SRC's parent to IMX8MP_SYS_PLL3_OUT ? > > Is the 400 MHz sufficient for audio-axi or does it have some negative > performance impact ? If the later, better send a patch to use PLL3 for audio- > axi . > > I'm adding Shengjiu to comment the audio part. With 400MHz, there is negative performance impact, as the audio AXI Clock is DSP's core clock. We have the requirement for normal drive mode, so 600MHz is required For audio AXI clock. Thanks. Best regards Shengjiu Wang > > > > > Thanks ! > > -- > Regards, > Liu Ying
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index d63564dbb12ca..19b9f764a0015 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -214,23 +214,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat t->mdiv, t->kdiv); } -static long clk_pll1416x_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - struct clk_pll14xx *pll = to_clk_pll14xx(hw); - const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; - int i; - - /* Assuming rate_table is in descending order */ - for (i = 0; i < pll->rate_count; i++) - if (rate >= rate_table[i].rate) - return rate_table[i].rate; - - /* return minimum supported value */ - return rate_table[pll->rate_count - 1].rate; -} - -static long clk_pll1443x_round_rate(struct clk_hw *hw, unsigned long rate, +static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_pll14xx *pll = to_clk_pll14xx(hw); @@ -285,22 +269,17 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { struct clk_pll14xx *pll = to_clk_pll14xx(hw); - const struct imx_pll14xx_rate_table *rate; + struct imx_pll14xx_rate_table rate; u32 tmp, div_val; int ret; - rate = imx_get_pll_settings(pll, drate); - if (!rate) { - pr_err("Invalid rate %lu for pll clk %s\n", drate, - clk_hw_get_name(hw)); - return -EINVAL; - } + imx_pll14xx_calc_settings(pll, drate, prate, &rate); tmp = readl_relaxed(pll->base + DIV_CTL0); - if (!clk_pll14xx_mp_change(rate, tmp)) { + if (!clk_pll14xx_mp_change(&rate, tmp)) { tmp &= ~SDIV_MASK; - tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv); + tmp |= FIELD_PREP(SDIV_MASK, rate.sdiv); writel_relaxed(tmp, pll->base + DIV_CTL0); return 0; @@ -319,8 +298,8 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, tmp |= BYPASS_MASK; writel(tmp, pll->base + GNRL_CTL); - div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | FIELD_PREP(PDIV_MASK, rate->pdiv) | - FIELD_PREP(SDIV_MASK, rate->sdiv); + div_val = FIELD_PREP(MDIV_MASK, rate.mdiv) | FIELD_PREP(PDIV_MASK, rate.pdiv) | + FIELD_PREP(SDIV_MASK, rate.sdiv); writel_relaxed(div_val, pll->base + DIV_CTL0); /* @@ -468,7 +447,7 @@ static const struct clk_ops clk_pll1416x_ops = { .unprepare = clk_pll14xx_unprepare, .is_prepared = clk_pll14xx_is_prepared, .recalc_rate = clk_pll14xx_recalc_rate, - .round_rate = clk_pll1416x_round_rate, + .round_rate = clk_pll14xx_round_rate, .set_rate = clk_pll1416x_set_rate, }; @@ -481,7 +460,7 @@ static const struct clk_ops clk_pll1443x_ops = { .unprepare = clk_pll14xx_unprepare, .is_prepared = clk_pll14xx_is_prepared, .recalc_rate = clk_pll14xx_recalc_rate, - .round_rate = clk_pll1443x_round_rate, + .round_rate = clk_pll14xx_round_rate, .set_rate = clk_pll1443x_set_rate, };
The pll1416x PLL so far only supports rates from a rate table passed during initialization. Calculating PLL settings dynamically helps in case e.g. multiple video outputs are used and they each need their own separate source of accurate pixel clock on i.MX8MP. In that case, e.g. PLL1416x PLL3 can be used as another Video PLL for another output. Extend the existing PLL1443x dynamic rate support to also apply to PLL1416x . Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Abel Vesa <abelvesa@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org --- drivers/clk/imx/clk-pll14xx.c | 39 ++++++++--------------------------- 1 file changed, 9 insertions(+), 30 deletions(-)