| Message ID | 20241112084542.1337314-6-suraj.kandpal@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [1/6] drm/i915/watermark: Initialize latency variable to appropriate value | expand |
On Tue, 2024-11-12 at 14:15 +0530, Suraj Kandpal wrote: > Increase the latency programmed into PKG_C_LATENCY latency to be > a multiple of line time which is written into WM_LINETIME. > > --v2 > -Fix commit subject line [Sai Teja] > -Use individual DISPLAY_VER checks instead of range [Sai Teja] > -Initialize max_linetime [Sai Teja] > > --v3 > -take into account the scenario when adjusted_latency is 0 [Vinod] > > --v4 > -rename adjusted_latency to latency [Mitul] > -fix the condition in which dpkgc is disabled [Vinod] > > WA: 22020299601 > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_wm.c | 21 ++++++++++++++++----- > 1 file changed, 16 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c > index ffc7dde86629..47c82aa2adf9 100644 > --- a/drivers/gpu/drm/i915/display/intel_wm.c > +++ b/drivers/gpu/drm/i915/display/intel_wm.c > @@ -157,8 +157,9 @@ intel_wm_compute_dpkgc_latency(struct intel_atomic_state *state, > struct intel_display *display = to_intel_display(state); > struct intel_crtc *crtc; > struct intel_crtc_state *new_crtc_state; > - u32 max_latency = LNL_PKG_C_LATENCY_MASK; > + u32 latency = LNL_PKG_C_LATENCY_MASK; > u32 added_waketime = 0; > + u32 max_linetime = 0; > int i; > bool fixed_refresh_rate = false; > > @@ -170,17 +171,27 @@ intel_wm_compute_dpkgc_latency(struct intel_atomic_state *state, > new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline) || > !new_crtc_state->vrr.enable) > fixed_refresh_rate = true; > + > + max_linetime = max(new_crtc_state->linetime, max_linetime); > } > > if (fixed_refresh_rate) { > - max_latency = skl_watermark_max_latency(i915, 1); > - if (max_latency == 0) > - max_latency = LNL_PKG_C_LATENCY_MASK; > + latency = skl_watermark_max_latency(i915, 1); > + > + /* Wa_22020299601 */ > + if (latency) { > + if (DISPLAY_VER(display) == 20 || DISPLAY_VER(display) == 30) > + latency = max_linetime * > + DIV_ROUND_UP(latency, max_linetime); new_crtc_state->linetime could be 0. So you need to protect division by 0 here? BR Vinod > + } else { > + latency = LNL_PKG_C_LATENCY_MASK; > + } > + > added_waketime = DSB_EXE_TIME + > display->sagv.block_time_us; > } > > - display->wm.dpkgc_latency = max_latency; > + display->wm.dpkgc_latency = latency; > display->wm.dpkgc_added_waketime = added_waketime; > > return 0;
> -----Original Message----- > From: Govindapillai, Vinod <vinod.govindapillai@intel.com> > Sent: Wednesday, November 13, 2024 3:50 PM > To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org; > intel-gfx@lists.freedesktop.org > Cc: Syrjala, Ville <ville.syrjala@intel.com> > Subject: Re: [PATCH 6/6] drm/i915/watermark: Modify latency programmed > into PKG_C_LATENCY > > On Tue, 2024-11-12 at 14:15 +0530, Suraj Kandpal wrote: > > Increase the latency programmed into PKG_C_LATENCY latency to be a > > multiple of line time which is written into WM_LINETIME. > > > > --v2 > > -Fix commit subject line [Sai Teja] > > -Use individual DISPLAY_VER checks instead of range [Sai Teja] > > -Initialize max_linetime [Sai Teja] > > > > --v3 > > -take into account the scenario when adjusted_latency is 0 [Vinod] > > > > --v4 > > -rename adjusted_latency to latency [Mitul] -fix the condition in > > which dpkgc is disabled [Vinod] > > > > WA: 22020299601 > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_wm.c | 21 ++++++++++++++++----- > > 1 file changed, 16 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_wm.c > > b/drivers/gpu/drm/i915/display/intel_wm.c > > index ffc7dde86629..47c82aa2adf9 100644 > > --- a/drivers/gpu/drm/i915/display/intel_wm.c > > +++ b/drivers/gpu/drm/i915/display/intel_wm.c > > @@ -157,8 +157,9 @@ intel_wm_compute_dpkgc_latency(struct > > intel_atomic_state *state, > > struct intel_display *display = to_intel_display(state); > > struct intel_crtc *crtc; > > struct intel_crtc_state *new_crtc_state; > > - u32 max_latency = LNL_PKG_C_LATENCY_MASK; > > + u32 latency = LNL_PKG_C_LATENCY_MASK; > > u32 added_waketime = 0; > > + u32 max_linetime = 0; > > int i; > > bool fixed_refresh_rate = false; > > > > @@ -170,17 +171,27 @@ intel_wm_compute_dpkgc_latency(struct > > intel_atomic_state *state, > > new_crtc_state->vrr.vmin == > > new_crtc_state->vrr.flipline) || > > !new_crtc_state->vrr.enable) > > fixed_refresh_rate = true; > > + > > + max_linetime = max(new_crtc_state->linetime, > > +max_linetime); > > } > > > > if (fixed_refresh_rate) { > > - max_latency = skl_watermark_max_latency(i915, 1); > > - if (max_latency == 0) > > - max_latency = LNL_PKG_C_LATENCY_MASK; > > + latency = skl_watermark_max_latency(i915, 1); > > + > > + /* Wa_22020299601 */ > > + if (latency) { > > + if (DISPLAY_VER(display) == 20 || > > +DISPLAY_VER(display) == 30) > > + latency = max_linetime * > > + DIV_ROUND_UP(latency, > > +max_linetime); > > new_crtc_state->linetime could be 0. So you need to protect division by 0 > here? Sure will do that here. Regards, Suraj Kandpal > > BR > Vinod > > > + } else { > > + latency = LNL_PKG_C_LATENCY_MASK; > > + } > > + > > added_waketime = DSB_EXE_TIME + > > display->sagv.block_time_us; > > } > > > > - display->wm.dpkgc_latency = max_latency; > > + display->wm.dpkgc_latency = latency; > > display->wm.dpkgc_added_waketime = added_waketime; > > > > return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c index ffc7dde86629..47c82aa2adf9 100644 --- a/drivers/gpu/drm/i915/display/intel_wm.c +++ b/drivers/gpu/drm/i915/display/intel_wm.c @@ -157,8 +157,9 @@ intel_wm_compute_dpkgc_latency(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(state); struct intel_crtc *crtc; struct intel_crtc_state *new_crtc_state; - u32 max_latency = LNL_PKG_C_LATENCY_MASK; + u32 latency = LNL_PKG_C_LATENCY_MASK; u32 added_waketime = 0; + u32 max_linetime = 0; int i; bool fixed_refresh_rate = false; @@ -170,17 +171,27 @@ intel_wm_compute_dpkgc_latency(struct intel_atomic_state *state, new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline) || !new_crtc_state->vrr.enable) fixed_refresh_rate = true; + + max_linetime = max(new_crtc_state->linetime, max_linetime); } if (fixed_refresh_rate) { - max_latency = skl_watermark_max_latency(i915, 1); - if (max_latency == 0) - max_latency = LNL_PKG_C_LATENCY_MASK; + latency = skl_watermark_max_latency(i915, 1); + + /* Wa_22020299601 */ + if (latency) { + if (DISPLAY_VER(display) == 20 || DISPLAY_VER(display) == 30) + latency = max_linetime * + DIV_ROUND_UP(latency, max_linetime); + } else { + latency = LNL_PKG_C_LATENCY_MASK; + } + added_waketime = DSB_EXE_TIME + display->sagv.block_time_us; } - display->wm.dpkgc_latency = max_latency; + display->wm.dpkgc_latency = latency; display->wm.dpkgc_added_waketime = added_waketime; return 0;
Increase the latency programmed into PKG_C_LATENCY latency to be a multiple of line time which is written into WM_LINETIME. --v2 -Fix commit subject line [Sai Teja] -Use individual DISPLAY_VER checks instead of range [Sai Teja] -Initialize max_linetime [Sai Teja] --v3 -take into account the scenario when adjusted_latency is 0 [Vinod] --v4 -rename adjusted_latency to latency [Mitul] -fix the condition in which dpkgc is disabled [Vinod] WA: 22020299601 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> --- drivers/gpu/drm/i915/display/intel_wm.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-)